“ High Electron Mobility InAs Nanowire Field-Effect Transistors ”

1. “High Electron Mobility InAs Nanowire Field-EffectTransistors” Shadi A. Dayeh, David P. R. Aplin, Xiaotian Zhou, Paul K. L. Yu,Edward T. Yu, and Deli Wang Small 3 (2): 326-332, 2007 Presented by Zachery Jacobson April 9, 2007

2. Outline • InAs Nanowire Fabrication • Fabrication without Au catalysts • Back-gated device fabrication • Results • Top-gated device fabrication • Results • Conclusions

3. InAs Nanowire Fabrication SEM • InAs nanowires are fabricated using MOCVD, with AsH3 and TMIn precursors • Time = 15 minutes • Temperature = 350°C • V:III ratio = 25 • Au colloid diameter = 40 nm • Nanowire diameter = 30-75 nm • Nanowire length = 20-30 um • Resulting nanowires are single-crystal Wurzite • Growth axis = [110] 20 um TEM HRTEM 50 nm 5 nm

4. Au catalyst-less InAs Nanowire Growth • Au forms deep level traps in Si, limiting the use of nanowires grown with Au catalysts in hybrid Nanowire/bulk Si systems • Using LP-MOCVD, InAs nanowires were grown on SiOx (x≈1) • No tapering or narrowing of the nanowires was found • The length of the nanowires is a function of the growth temperature, and is fairly short • E-beam lithography can also be used to pattern “islands” of SiOx, that define where nanowires will grow • Si and InP(111)B substrates were used, although best results were found with InP(111)B substrates B. Mandl, et al, Nano Letters 6 (8): 1817-1821, 2006

5. Back-gated Device Fabrication • InAs nanowires were sonicated from a growth substrate in ethanol and transferred to a 600 nm SiO2/n+ Si substrate • E-beam lithography was used to pattern 15 nm Ti/85 nm Al contacts for the source and drain

6. Back-Gate Results VDS = 0.5 V • uFE=2740 cm2V-1 s-1 • Transconductance was found to be 2 uS • This is found to be comparable to a free electron gas on the nanowires surface • Due to surface states on SiO2 substrate and S/D gate coupling due to global back gate

7. Top-gated Device Fabrication • Same steps as back-gated device followed • Gate was defined using e-beam lithography using 100 nm sputtered SiO2 and 100 nm of Au gate electrode • Source drain separations varied from 0.5um to 4um

8. Top-Gate Results • Analysis was comprehensive • Contact resistance was calculated to be 1-10 kΩ, and 1 kΩ was used to show worst-case mobility • 2-D device simulators were used to calculate gate capacitance

9. Conclusions • InAs nanowires can be easily fabricated using MOCVD technology with or without metal catalyst particles • This paper presents a detailed procedure for collecting mobility values while accounting for contact and series resistance, as well as parasitic capacitances • InAs nanowires were found to have great potential as n-type NW FETs Thank you for your time! Questions?