P o l y morphic Electronics

1. Polymorphic Electronics Adrian Stoica, Ph.D. Jet Propulsion Laboratory California Institute of Technology 818 354 2190 adrian.stoica@jpl.nasa.gov

2. Essence • A new technology/paradigm based on electronic designs with superimposed built-in multiple functionality is suggested. Individual functions surface enabled by global controls, such as temperature, VDD, and EM field, controls that can quasi-instantly change the functionality over the entire computing circuit. • The technology has potential for defense/ security/ intelligence applications.

3. Benefits for defense/security/intelligence communities • Info Ops is key capability for force (Joint Vision 2020). • “The ability to understand secret communications of our foreign adversaries while protecting our own…gives our nation a unique advantage” NSA Mission Statement • Critical for ensuring Info/decision superiority. (AS) • Polymorphics provides a new way to obtain circuits with one or more conceived “extra” functions in addition to the “main” function of the circuit. The “extras” can be activated under certain conditions or can coexist. Uses of the “extras”: • An authentication signature / watermark • Observable function is a cover • Protection from reverse engineering – the real operational function of the circuit shows up only in special conditions – extra layer of protection • Protection from unauthorized usage –biometric info part of circuit design • Additional communication channel

4. Potential for defense/security/intelligence applications • It allows for a built-in reactive behavior surfacing/taking control in specified conditions: for example, smart fuses in which the increased temperature triggers a new functionality of the guidance electronics. • Systems that rapidly morph between functions. Fast. Without switching overhead. • More compact multi-functional designs.

5. Content • Evolvable Hardware • What it is, progress, challenges and efforts addressing them • Polymorphic Electronics • Experiments with various controls (T, VDD, In). Novelty. • Potential for defense/security/intelligence • Plan to develop the technology

6. Evolvable Hardware = Reconfigurable HW + Evolutionary Algorithms • Evolvable Hardware (EHW) is HW that self-configures under the control of evolutionary algorithms • Evolutionary Algorithms are search technique inspired by biological evolution. More general EHW can use other search techniques. • Hardware means electronics, antennas, MEMS, etc. • DARPA supports JPL EHW in the context of Adaptive Computing, NASA’s main interest is for self-repair, survivability in extreme environments. • After fixed and reconfigurable HW, evolvable/self-configurable HW is a new HW generation with increased flexibility.

7. JPL EHW Motivation : enable long-life survivable spacecraft Dramatic changes in hardware/environment, e.g. in case of faults or need for new functions, may require in-situ synthesis of a totally new hardware configuration. Survivability: Maintain functionality coping with changes in HW characteristics Versatility: Create new functionality required by changes in requirements or environment EHW • Radiation impacts • Temperature variations • Aging • Malfunctions, etc. New functions required for new mission phase or opportunity Up-link new functions for re-planned mission Accurate model of hardware is not available after launch JPL develops space HW that can evolve

8. EHW and Automated Synthesis Status of traditional Automated Synthesis (AS) • AS for Digital is not totally automated (from high level to low level) • AS doesn’t exist for Analog and Mixed Signal • AS doesn’t include the HW in the optimization loop Automated Synthesis EHW offers an advancement over traditional AS techniques AS SOA EHW Automated Synthesis by EHW • Allows development of hybrid /on chip systems • It is fully automated • It works in both SW and HW • It does not rely on models, and can cope with faults, changes, etc.

9. Evolutionary synthesis and adaptation of electronic circuits Chromosomes Conversion to a circuit description • Evolutionary Algorithm • Genetic search on a population of chromosomes • select the best designs from a population • reproduce them with some variation • iterate until the performance goal is reached. 10110011010100 01110101101111 11011011010110 Models of circuits Control bitstrings Extrinsic evolution Simulators (e.g., SPICE) Evaluate individual responses and assess their fitness Target response Intrinsic evolution Circuit response Reconfigurable hardware Potential electronic designs/implementations compete; the best ones are slightly modified to search for even more suitable solutions

10. The JPL EHW testbed allows evolution in SW, HW and mixed SW/HW Link to Hardware Evaluation Link to Software Evaluation Evolutionary Reconfiguration Mechanism (PGAPack) GUI Database Chromosome and circuit info SW Tool: EHWPack HWresources: PC + NI HW/SW, Supercomputer LabView A/D 256-processor HP Exemplar running SPICE 3f5 Digital I/O D/A Reconfigurable hardware Chips under test SW model of the hardware The user can draw a function using the graphical tablet. A few minutes later the hardware has evolved(automatically synthesized) a circuit that provides the function

11. ... PTA00 PTA08 ... PTA16 PTA09 Array of PTAs ... PTA56 PTA64 Transistor Control Analog I/O Digital I/O Steps in building evolution oriented devices FY99 FY00/01 FY01 EP – Evolutionary Processor Evolve circuits under SW-GA (PC) control EC- Evolvable Chip PTA EP Programmable Transistor Array 1 closes the switch 2 chips on PCI card Reconfigurable FPTA Chip new chip includes an Active Pixel Sensor Vision sensor with ~10000 transistors 100011….1111 We are currently developing a stand-alone evolvable system We have built several programmable devices reconfigurable at transistor level – Field Programmable Transistor Arrays - on which we are evolving circuits.

12. Example of evolved non-conventional computational circuits Fuzzy-Neuron Circuit S(x,y) x y • Uses two FPTA cells (16 transistors) • Provides a compact implementation Target Output S Circuit Output Input Y Input X Evolution can easily synthesize circuits characterized by complicated formulas, for which analog designers do not have design guidelines

13. Examples of evolved circuits • Computational circuits: gaussian, neurons • Filters, • A/D, D/A • adaptive and reconfigurable circuits: fuzzy neuron • polymorphic gates • multiplier • logic circuits • MOVIE • EHW-based Automatic synthesis has been successful for small circuits • Automatic parametric optimization is becoming successful in commercial applications

14. Scalability Existence/convergence of optimal solution Satisfying real world requirements loads, power Low reliability/safety of evolved solution Un-predictability Lack of evolution-oriented devices Hierarchy Representations, adaptive GA parameters Smart fitness Evolve sensors rather than controls ? Develop our own chips D Q Q Clk Challenges …and how we address them

15. DAC: evolving a scalable design 2Bit DAC 3Bit DAC 4Bit DAC We demonstrated a scalable approach based on encapsulation and block reuse

16. VDD Registers Pixel Array CLK Row decoder Row logic Difference Analog Out Analog readout Digital in Amplifier Control logic ADC Parallel/ serial Digital Out DAC Column decoder GND Evolvable vision sensors • Smart sensing • – evolve reconfigurable sensors We are replacing fixed dedicated analog processing with self-reconfigurable ones. Our first target is an evolvable vision chip currently under fabrication.

17. Evolving randomizers • Synthesis of Random Number Generators on FPGAs is an excellent choice for evolutionary design: there are no design guidelines for new RNG, but measures of randomness do exist. • Uses in cryptographic applications – NSA. • Implementation status • Completed design and validation of a VHDL implementation for a pseudo random number generator. The design is being ported to the FPGA board. • Integrated the DIE HARD software suite that will be used in the evaluation of pseudo random generator into the EHW test bed • Will replace with analog chip to try evolution of TRNG Execute the Genetic Algorithm and Evaluate sets of pseudo random numbers using DIE HARD software suite A/D Digital I/O D/A Generate sets pseudo random numbers Xilinx Virtex FPGA Board

18. Evolvable antenna system Motivation: adapt to changes in environment as well as damage • Demonstrated • Automatic evolution of reconfigurable antennas • Antenna adaptation to different barriers, orientations, frequencies, and loss of control • Superior performance over conventional antenna Antenna Barrier 10  750 cm RF Generator 0.4 30cm RF cable RF Receiver PC Audio cable Control cables USB cable DAQPad 6507 Evolvable antenna concept by Linden & Stoica Work by Dr. Linden of LIR with JPL funding

19. Vdd I2 Out I1 I2 Expand temperature operational range through circuit reconfiguration Demonstrated that evolution can automatically (on-chip, in-situ) find circuit solutions that recover lost functionality, thus expanding the operational envelope of current devices Radiation -200 C Bulk CMOS +250 C Temperature Tests on prototype chips 3.3V Evolved@27C Degradation as measured@240 Recovered by evolution @240C Future work: • Expand temperature range to [-230 +460C]. • Add radiation. • Evolve new circuit designs for high temperatures I1

20. Polytronics • Polytronics (Polymorphic electronics) refers to a novel, special type of electronic devices and circuits, characterized by built-in superimposed multiple functionality.

21. Controls for Polytronics • Polymorphic circuits could selectively exhibit/change their function as a result of changes in control parameters such as temperature, light, radiation, power supply voltage or other variable that produces variations to the device characteristics. More traditionally, the function can be changed by special control electrical signals. • Example: A two input circuit that performs logic AND at room temperature (e.g. at 27C) and logic OR when heated (e.g. at 90C).

22. The evolutionary approach to polymorphic design • Use evolvable hardware (EHW) • Impose a set of different requirements/tests for several different operational regions of interest (e.g. a desired circuit behavior at 27C and another desired behavior at 90C). Use a fitness function that ensures the mutual satisfaction of the two requirements. (E.g. the global fitness is calculated as the weighted sum of fitnesses at 27C and 90C)

23. Experiments • Control by temperature • Control by dedicated input signal Vmorph • Control by voltage supply level VDD • Planned/ongoing experiments • More complex functionality

24. Control by temperature Two categories of experiments were performed: • using a free/unconstraint architecture (SW) • using the Field Programmable Transistor Array architecture (SW + HW) Test chamber used for high temperature experiments

25. Evolutionary design of temperature controlled polymorphic logic gates Objective: Design a circuit that performs the AND function at T1, and OR at T2 Example: In1 In2 In1 In1 Out Out AND OR In2 In2 AND 27C T2=90C T1=27C OR 90C It is the exactly the same circuit -only its function changes with temperature!

26. Topology and circuit response resulted from the unconstraint (SW) search for a polymorphic temperature controlled AND/OR gate Unconstrained representation AND @ 27oC OR @ 125oC Transient analysis, a delay in reaching the level can be noticed.

27. Circuit and response for FPTA-evolved polymophic gate at two temperatures of interest Out In2 In1 AND at 5oC – OR at 90oC Logic threshold for VDD = 3.3V OR (90oC) Output Voltage Output is ‘1’ Topology of evolved circuit mapped on two FPTA cells Dark lines indicates closed switches Output is ‘0’ (AND 5oC) (1,1) (0,0) (0,1) (1,0) Time and input combination X-axis is the time axis. Each combination of input values is kept for 2.5ms. The Y-axis shows the voltage output for each combination.

28. 1 0 1 0 0 1 1 1 0 00 01 10 11 10OC 20OC 30OC 40OC 50OC 60OC Response of the evolved polymorphic gate: more detail for its variation as a function of temperature 1.65V threshold between logical levels 0 and 1 As the temperature changes the circuit gradually morphs from AND to OR

29. Control by dedicated input signal Vmorph Topology and response of evolved AND/OR gate Fitness of candidate circuits increases over generations Vmorph= 3.3V AND When Vmorphchanges from 3.3V to 0V the function changes from AND to OR Vmorph = 0V OR

30. Evolved OR/AND/XOR polymorphic gatewith multi-level control Fitness of candidate circuits increases over generations • Uses a control input Vmorph • - Gate is OR if Vmorph = 0V • - Gate is XOR if Vmorph =1.5V • - Gate is AND if Vmorph = 3.3V OR AND XOR A single multi-level signal Vmorph controls three functional instances. Solution is rather compact.

31. Evolved OR/AND polymorphic with supply voltage (VDD) control Original specifications: • OR gate for Vdd = 3.3V; • AND gate for Vdd = 1.2V; • Load C = 50pf • 8 transistors • - Gate is OR for VDD = 3.3V • - Gate is XOR for VDD =1.2V

32. Summary of Innovative Claims - Proposed a novel multi-functional systems paradigm relying on designs with superimposed built-in multiple functionality, selectively exhibiting one of the built-in functions under the control of an external parameter. - Quasi-instant control/functional change of an entire processing circuitry that depends on global controls, such as the supply voltage, temperature, EM field etc. Can expand to other – non-electronic – devices. The sensor is the switchTM .  • Multi-function selection with a single analog/multi-valued signal. Connecting all all control signals could provide a similar change all across the computing platform, while selective control and/or variable timing could help more refined morphing capability. Allows analog/gradual/morphing change between functions.

33. Polymorphic devices for defense/security/intelligence applications • Polymorphics provides a new way to obtain circuits with one or more conceived “extra” functions in addition to the “main” function of the circuit. The “extras” can be activated under certain conditions or can coexist. Uses of the “extras”: • An authentication signature / watermark • Observable function is a cover - • Protection from reverse engineering – the real operational function of the circuit shows up only in special conditions – extra layer of protection. • Protection from unauthorized usage –biometric info part of circuit design. The circuit performs main function only when its senses a certain biometric signal, e.g. an array of voltages generated from fingerprint sensing “biases” properly components of the circuit, tuning it for the proper function • Additional communication channel

34. Polymorphic devices for defense/security/intelligence applications • It allows for a built-in reactive behavior surfacing/taking control in specified conditions: Smart skin adapting to temperature or lighting conditions. The sensing and the processing become one. • Systems that rapidly morph between functions. Fast. Without switching overhead. Eliminate time overhead of programming 10M gates as in Xilinx II Pro. Or eliminate the resource overhead of the swap memory. • More compact multi-functional designs. AND/OR/XOR takes roughly 20 transistors plus switching logic. We did it with 10 and one multi-level control. • Several signatures at different temperatures can be earmarked. Is is truly from a trusted source? I test it at VDD = 3.3V (or 27C) and I get the signature NSA, I test itVDD = 1.8V (or 90C) with signature DARPA. Etc. • Adaptive info processing, Environment aware, Medium Aware processing – algorithm/processing structure changes as needed with the temperature e.g.power aware DAC 16Bit when battery is full, 8Bit at low. • Truly Adaptive Devices – Built-in functional changes

35. Plans for future work • Demonstrate a range of polymorphic circuits, in simulations and on a prototype chip • Develop a methodology to design systems based on polymorphic circuits • Develop techniques to control morphing by a variety of techniques such as: power supply, temperature, electromagnetic field • Seek customers and build relevant circuits

36. Extending the polymorphic idea to non-standard devices • Going beyond CMOS • The more nonlinearities and sensitivity the characteristic of a devices has, the more suitable it becomes for polymorphics • Derive and use Spice/VHDL-A models for a variety of devices (e.g. RTD, SET,etc) including temperature dependency • A memory device –input some info/control and retrieve a function/algorithm

37. Risks – What ifs… • The approach does not scale ? • There is no methodology to design large systems? • Can lead to unstable/easy to damage designs? • Identify niche applications

38. Conclusion • A new way of looking at multi-functional circuits • A new way to hide functions, protect devices, build smarts