VLSI Testing

1. VLSI Testing 李昆忠 Kuen-Jong Lee 06-2757575 X 62371 kjlee@mail.ncku.edu.tw September 13, 2005

2. IC Design & Production Flow 1. Design House 2. Foundry 3. Foundry or Testing House 4. Packaging House 5. Testing House IC Design & Design-for-Test Wafer Manufacturing Wafer Testing Packaging Final Testing Shipping

3. Course Objectives • To learn about • The role and cost of testing in VLSI circuits & systems • The types of faults expected and how to model them • Fundamental techniques for detecting defects in VLSI circuits • Algorithms for automatic test generation • Schemes for designing circuits to be easily testable and/or with self-test capability • Hands-on experience with state-of-the-art computer-aided-test tools in the laboratory • How to survey state-of-the-art research topic

4. Contents • Introduction • Fault Modeling • Fault Simulation • Test Generation • Design for Testability • Boundary Scan • Built-in-Self-Test • Memory Testing • CPU Tesing • System-on-a-Chip Testing • Special topics (IDDQ testing, Test compression, Analog testing, etc.)

5. References • Essentials of Electronic Testing: for Digital, Memory & Mixed-Signal VLSI Circuits, 2000, by M. Bushnell & V.D. Agrawal. Kluwer, Academic Publishers. • Digital System Testing and Testable Design, 1990, By M. Abramovici, M.A. Breuer & A.D. Friedman. • Digital Logic Testing and Simulation, By A. Miczo, 2nd Edition, John Wiley & Sons, 2003, ISBN:0-471-43995-9 • Proceedings in ≧ 30 IEEE Conferences/ Symposiums/Workshops on testing each year. • International Journals: IEEE T-CAD, T-VLSI, T-C&S, T-Computers, JETTA, etc.

6. Class Requirements & Grading Prerequite: Logic design, Electonics I & II, Electrical Circuits, Basic VLSI design concepts • Homeworks & Exercises 20-35% • Midterm & Final Exams 50-70% • Final Report 20-30% Teaching Assistants: 謝東佑, 許宏銘 (62400 X 827, 829, EE92A29,A31) {sty95, hhm95}@beethoven.ee.ncku.edu.tw WWW 網站: http://beethoven.ee.ncku.edu.tw/testlab/course/testing_course/