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Insightful Analysis of 0.1µm CMOS Layout Design

Explore the evolution of CMOS technology scale-down, design trends, MOS devices, signal propagation, and embedded memories in this comprehensive study. Discover the impact of advancements in technology on layout design.

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Insightful Analysis of 0.1µm CMOS Layout Design

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  1. An Illustration of 0.1µm CMOS layout design on PC Etienne Sicard, Sonia Bendhia etienne.sicard@insa-tlse.fr sonia.bendhia@insa-tlse.fr http://intrage.insa-tlse.fr/~etienne

  2. Summary 1. The technology scale down 2. Design trends 3. The MOS device 4. CMOS cell design 5. Signal propagation 6. Embedded Memory 7. SOI E. Sicard - EWME'02 Vigo

  3. Introduction to µ-Electronics on PC MSK, PROF, 3D Introduction to CMOS design on PC Microwind, Dsch IC 1. The technology scale down 10 years of evolution 1992 2002 • 0.7µm, 2 metal layers • Up to 100K transistors, 50MHz • 0.12µm, 7 metal • Up to 500MT, 1.5GHz E. Sicard - EWME'02 Vigo

  4. 1992-2002 • Slightly decreased 1014 neurons • Slightly increased number of students • Endless fight against obsolete teaching • Constant 24H per day 8 layers 7 layers 1V 2V 1. The technology scale down 1992 2000 2003 0.7 µm 90nm 0.18 µm l Devices 6 nMOS, 6pMOS 1 nMOS, 1pMOS 3 nMOS, 3pMOS Interconnects 2 layers 5V Frequency 1.5GHz 50MHz 500MHz E. Sicard - EWME'02 Vigo

  5. RF Link Controller Code Manager RS Host Interface Layout design Microwind 2. Design trends Complexity (Millions transistors) Technology always ahead 100 System design 10 IP design Logic design 1.0 0.1 0.01 1992 1994 1996 1998 2000 2002 2004 E. Sicard - EWME'02 Vigo

  6. Model parameters 1000 Bsim2 Bsim4 Bsim 100 • BsimSOI Level 2 MM9 Level 1 10 Level 3 1 1970 1980 1990 2000 2010 2. Design trends Core BSIM3 BSIM4 level 3 BSIM Physical SystemC VHDL, Verilog VHDL-Ams Structural Interface IBIS v2 IBISv3 IBIS-ML IBIS Physical 1995 1997 1999 2001 2003 E. Sicard - EWME'02 Vigo

  7. 3. The MOS devices Dependence of Id vs. Length Impact ionization at high Vds Important Ioff current for small Length Complex dependence of Vt vs. Length E. Sicard - EWME'02 Vigo

  8. MRam RF New physical properties in EEPROM and MRam 3. The MOS devices Ultra High Speed Low Leakage EEProm High Voltage High Speed Application-oriented MOS device Same basic mechanism E. Sicard - EWME'02 Vigo

  9. Small Ion reduction Ioff ~100pA Low Leakage High Speed Default MOS device, high VT low leakage (<1nA) High current MOS, low VT Shorter channel L=100nm, high leakage (Critical path) Demo 3. The MOS devices Ioff ~10nA E. Sicard - EWME'02 Vigo

  10. 4. CMOS cell design Stacked vias Salicide/unsalicide (Large R) but… Antenna effects Contact parasitic effect (20 ) E. Sicard - EWME'02 Vigo

  11. Volt 2 3 5 4 1.5 2 3 1 2 1 0.5 1 0 0 0 0 0.5 1.0 1.5ns 0 1 2 3ns 0 0.25 0.5 0.75 1.0ns Repeaters help to propagate signals at long distance 3Rx3C=9RC (680ps) 3mm 3RC+2tgate (380ps) 1mm 1mm 1mm Demo 5. Signal propagation Volt Volt 0.35 µm 0.18µm 0.7 µm Cu Al Al E. Sicard - EWME'02 Vigo

  12. Very large noise, close from fault • Low K to reduce coupling • Long distance routing is forbidden (Critical routing length 2mm in 0.12µm) 5. Signal propagation 0.7µm Small coupling 0.12µm Strong coupling E. Sicard - EWME'02 Vigo

  13. Non volatile Volatile eDRAM SRAM ROM EEPROM FRAM 6. Embedded Memories • 80% of a system-on-chip • Bottleneck for bandwidth Cmos Embedded memories E. Sicard - EWME'02 Vigo

  14. CS CB 6. Embedded Memories Parasitic capacitance: 2fF Specific capacitance: 3-30fF E. Sicard - EWME'02 Vigo

  15. VDD Create a small channel VDD Cannot create channel Electrons injected in the floating gate by tunneling Demo 6. Embedded Memories E. Sicard - EWME'02 Vigo

  16. Fully or partially depleted? Kink effect 7. SOI The next major evolution? CMOS compatible Less distance between nMOS and pMOS Less capacitance Less leakage >50% faster circuits E. Sicard - EWME'02 Vigo

  17. Conclusion • The technology scale down has been illustrated • Design trend towards higher levels of abstraction • More MOS options oriented to applications in 0.1µm technology • Increased interconnect layers improve density but many issues • RC delay & crosstalk illustrated • Embedded memories have several design styles and technological option • Substrate below 0.1µm should be in SOI • Lots of educational messages illustrated in Microwind PC tool • Freeware available at http://intrage.insa-tlse.fr/~etienne E. Sicard - EWME'02 Vigo

  18. References • International Roadmap for Semiconductors • MOSFET models for SPICE simulations (BSIM3v3, BSIM4) Liu,Wiley, 2001 • Low-voltage SOI CMOS Devices, Kuo, Wiley, 2001 • Introduction to VLSI circuits & systems Uyemura, Wiley, 2002 • CMOS circuit design Layout & simulation, Baker, IEEE press, 1998 • IBM press releases & web site E. Sicard - EWME'02 Vigo

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