Overview

1. Overview • Last lecture • Ripple and Carry-Lookahead Adders • Today • ALU • An Introduction to Hardware Description Languages (HDL) CSE 370 – Winter 2002 - Hardware Description Languages - 1

2. Cin Cin A0 S0 @2 B0 S0 @2 A0 C1 @3 C1 @2 B0 A1 S1 @4 B1 S1 @3 A1 C2 @3 C2 @4 B1 A2 S2 @4 B2 S2 @5 A2 C3 @3 C3 @6 B2 A3 S3 @4 B3 A3 S3 @7 C4 @3 C4 @3 B3 Cout @8 Carry-lookahead implementation (cont’d) • Carry-lookahead logic generates individual carries • sums computed much more quickly in parallel • however, cost of carry logic increases with more stages CSE 370 – Winter 2002 - Hardware Description Languages - 2

3. Cin A0 S0 @2 B0 A1 S1 @4 B1 A2 S2 @4 B2 A3 S3 @4 B3 Gi, Pi, available at time 1 GiPi available at time 2 GiPi + GjPj available at time 3 GP0 available at time 2 GG0 available at time 3 Gi = Ai Bi Pi = Ai xor Bi G0 + P0 C0 G1 + P1 G0 + P1 P0 C0 G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 GP0= P3 P2 P1 P0 GG0= G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0+ P3 P2 P1 P0 C0 CSE 370 – Winter 2002 - Hardware Description Languages - 3

4. 4 4 4 4 4 4 4 4 4-bit Adder 4-bit Adder 4-bit Adder 4-bit Adder A[15-12] B[15-12] A[11-8] B[11-8] A[7-4] B[7-4] A[3-0] B[3-0] C12 C8 C4 C0 P G P G P G P G @0 4 4 4 4 S[15-12] S[11-8] S[7-4] S[3-0] @8 @8 @7 @4 @3 @2 @2 @3 @2 @3 @2 @3 @5 @5 @4 P3 G3 P2 G2 C2 P1 G1 C1 P0 G0 C3 C0 C16 C0 C4 Lookahead Carry Unit @4 @0 P3-0 G3-0 @3 @5 Carry-lookahead adderwith cascaded carry-lookahead logic • Carry-lookahead adder • 4 four-bit adders with internal carry lookahead • second level carry lookahead unit extends lookahead to 16 bits CSE 370 – Winter 2002 - Hardware Description Languages - 4

5. 4-bit adder[7:4] C8 1 adderhigh C8 0 4-bit adder[7:4] adder low 1 0 1 0 1 0 1 0 1 0 C0 C4 4-Bit Adder[3:0] five2:1 mux S6 S1 C8 S7 S5 S4 S3 S2 S0 Carry-select adder • Redundant hardware to make carry calculation go faster • compute two high-order sums in parallel while waiting for carry-in • one assuming carry-in is 0 and another assuming carry-in is 1 • select correct result once carry-in is finally computed CSE 370 – Winter 2002 - Hardware Description Languages - 5

6. Arithmetic Logic Unit • Inputs: n-bit words • A = An-1An-2… A0; B = Bn-1Bn-2… B0; Carry-in C0 • Output: n+1-bit word + some signals (overflow, zero, etc.) • F = FnFn-1…F0 where Fn is in fact carry-out • Control inputs. For example: • M = 0 “logic” (i.e., bit wise) operations • M = 1 “arithmetic” (with carry) operations • Other control bits Sm,Sm-1,…,S0 for selecting particular “opcodes” CSE 370 – Winter 2002 - Hardware Description Languages - 6

7. ALU specification (1-bit slice) M = 0, logical bitwise operations S10011 S00101 FunctionFi = AiFi = not AiFi = Ai xor BiFi = Ai xnor Bi Commentinput Ai transferred to outputcomplement of Ai transferred to outputcompute XOR of Ai, Bicompute XNOR of Ai, Bi M = 1, C0 = 0, arithmetic operations 0011 0101 F = AF = not AF = A plus BF = (not A) plus B input A passed to outputcomplement of A passed to outputsum of A and Bsum of B and complement of A M = 1, C0 = 1, arithmetic operations 0011 0101 F = A plus 1F = (not A) plus 1F = A plus B plus 1F = (not A) plus B plus 1 increment Atwos complement of Aincrement sum of A and BB minus A logical and arithmetic operationsnot all operations appear useful, but "fall out" of internal logic CSE 370 – Winter 2002 - Hardware Description Languages - 7

8. M011 S1001100110011 S0010101010101 CiXXXXXXXXXXXX000000000000111111111111 Ai0101001100110101001100110 10100110011 BiXXXX01010101XXXX01010101XXXX01010101 Fi011001101001011001101001100110010110 Ci+1XXXXXXXXXXXXXXXX00010100011001111101 Arithmetic logic unit design (cont’d) • Sample ALU – truth table CSE 370 – Winter 2002 - Hardware Description Languages - 8

9. \S1 \Bi [35] M Ci Ci [33] \Co Ci Co [30] M S1 Bi [30] [33] [33] Fi [33] \Co M [30] Ci [35] [30] S0 Ai [30] \Co \[30] \[35] Arithmetic logic unit design (cont’d) • Sample ALU – multi-level discrete gate logic implementation (via a CAD tool) 12 gates CSE 370 – Winter 2002 - Hardware Description Languages - 9

10. S1 Ai Bi S0 Ci M X1 A1 A2 X2 A3 A4 X3 O1 Ci+1 Fi Arithmetic logic unit design (cont’d) • Sample ALU – clever multi-level implementation (see Katz for details) • first-level gates • use S0 to complement Ai S0 = 0 causes gate X1 to pass Ai S0 = 1 causes gate X1 to pass Ai' • use S1 to block Bi S1 = 0 causes gate A1 to make Bi go forward as 0 (don't want Bi for operations with just A) S1 = 1 causes gate A1 to pass Bi • use M to block Ci M = 0 causes gate A2 to make Ci go forward as 0 (don't want Ci for logical operations) M = 1 causes gate A2 to pass Ci • other gates • for M=0 (logical operations, Ci is ignored) • Fi = S1 Bi xor (S0 xor Ai) • = S1'S0' ( Ai ) + S1'S0 ( Ai' ) + S1 S0' ( Ai Bi' + Ai' Bi ) + S1 S0 ( Ai' Bi' + Ai Bi ) • for M=1 (arithmetic operations) • Fi = S1 Bi xor ( ( S0 xor Ai ) xor Ci ) = • Ci+1 = Ci (S0 xor Ai) + S1 Bi ( (S0 xor Ai) xor Ci ) = • just a full adder with inputs S0 xor Ai, S1 Bi, and Ci CSE 370 – Winter 2002 - Hardware Description Languages - 10

11. Summary for examples of combinational logic • Combinational logic design process • formalize problem: encodings, truth-table, equations • choose implementation technology (ROM, PAL, PLA, discrete gates) • implement by following the design procedure for that technology • Binary number representation • positive numbers the same • difference is in how negative numbers are represented • 2s complement easiest to handle: one representation for zero, slightly complicated complementation, simple addition • Circuits for binary addition • basic half-adder and full-adder • carry lookahead logic • carry-select • ALU Design • specification, implementation CSE 370 – Winter 2002 - Hardware Description Languages - 11

12. Hardware description languages (HDL) • Describe hardware at varying levels of abstraction (HDLs are HLLs) • chip densities increase hence design complexity increases • Structural description • textual replacement for schematic (because of increase in complexity) • hierarchical composition of modules from primitives • Behavioral/functional description • describe what module does, not how • synthesis generates circuit for module • Simulation semantics CSE 370 – Winter 2002 - Hardware Description Languages - 12

13. HDLs • Abel (circa 1983) - developed by Data-I/O • targeted to programmable logic devices (PLAs, PALs etc.) • not good for much more than state machines • ISP (circa 1977) - research project at CMU • simulation, but no synthesis • Verilog (circa 1985) - developed by Gateway (now part of Cadence) • similar to Pascal and C • delays is only interaction with simulator • fairly efficient and easy to write • IEEE standard • VHDL (circa 1987) - DoD sponsored standard • “V” is for “VHSIC” (very high speed integrated circuit) • similar to Ada (emphasis on re-use and maintainability) • simulation semantics visible • very general but verbose • IEEE standard CSE 370 – Winter 2002 - Hardware Description Languages - 13

14. Verilog • Supports structural and behavioral descriptions • Structural • explicit structure of the circuit • e.g., each logic gate instantiated and connected to others • Behavioral • program describes input/output behavior of circuit • many structural implementations could have same behavior • e.g., different implementation of one Boolean function • We’ll only be using behavioral Verilog • rely on schematic for structural constructs CSE 370 – Winter 2002 - Hardware Description Languages - 14

15. Verilog capabilities (overview) • Hierarchical design using instantationof modules • A module, like a procedure in a C-like language, has a name, input/output ports, and a body • A module is not called like a procedure. It isinstantiated. • Inputs are monitored. Upon change, the output is changed. • Can be done continuously, or under some conditions • Output can be instantaneous, or after some delay • The module stays around for the lifetime of the program CSE 370 – Winter 2002 - Hardware Description Languages - 15

16. Structural model module xor_gate (out, a, b); input a, b; output out; wire abar, bbar, t1, t2; inverter invA (abar, a); inverter invB (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2); endmodule CSE 370 – Winter 2002 - Hardware Description Languages - 16

17. Simple behavioral model • Continuous assignment; Input continuously monitored; Can be used for combinational circuits Required key word Name Port list module and_gate (out, in1, in2); input in1, in2; output out; reg out; assign #2 out = in1 & in2; endmodule delay from input changeto output change CSE 370 – Winter 2002 - Hardware Description Languages - 17

18. Simple behavioral model • always block; “infinite-loop”-like assignment; output changes every time input changes module and_gate (out, in1, in2); input in1, in2; output out; reg out; always @(in1 or in2) begin #2 out = in1 & in2; end endmodule simulation register - keeps track ofvalue of signal specifies when block is executed ie. triggered by which signals CSE 370 – Winter 2002 - Hardware Description Languages - 18

19. Module Hierarchy (Basic idea) • Connect modules together to form larger modules • Example: • Build an AND gate by 2 NAND gates in series module NAND2 (in1, in2, out); input in1, in2; output out; assign out = ~(in1 & in2); endmodule module AND2(in1,in2,out); input in1,in2; output out; wire w1; // to connect the 2 NAND's NAND2 nand1(in1,in2,w1); NAND2 nand2(w1,w1,out); endmodule CSE 370 – Winter 2002 - Hardware Description Languages - 19

20. Driving a simulation module stimulus (a, b); output a, b; reg [1:0] cnt; initial begin cnt = 0; repeat (4) begin #10 cnt = cnt + 1; $display ("@ time=%d, a=%b, b=%b, cnt=%b", $time, a, b, cnt); end #10 $finish; end assign a = cnt[1]; assign b = cnt[0];endmodule 2-bit vector initial block executed only once at startof simulation (in contrast with “always”) print to a console directive to stop simulation CSE 370 – Winter 2002 - Hardware Description Languages - 20

21. Complete Simulation • Instantiate stimulus component and device to test in a schematic CSE 370 – Winter 2002 - Hardware Description Languages - 21

22. Comparator Example module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign #5 Equal = (A & B) | (~A & ~B); assign #3 Alarger = (A & ~B); assign #3 Blarger = (~A & B); endmodule CSE 370 – Winter 2002 - Hardware Description Languages - 22

23. More Complex Behavioral Model module life (n0, n1, n2, n3, n4, n5, n6, n7, self, out); input n0, n1, n2, n3, n4, n5, n6, n7, self; output out; reg out; reg [7:0] neighbors; reg [3:0] count; reg [3:0] i; assign neighbors = {n7, n6, n5, n4, n3, n2, n1, n0}; always @(neighbors or self) begin count = 0; for (i = 0; i < 8; i = i+1) count = count + neighbors[i]; out = (count == 3); out = out | ((self == 1) & (count == 2)); end endmodule CSE 370 – Winter 2002 - Hardware Description Languages - 23

24. Hardware Description Languages vs. Programming Languages • Program structure • instantiation of multiple components of the same type • specify interconnections between modules via schematic • hierarchy of modules (only leaves can be HDL in DesignWorks) • Assignment • continuous assignment (logic always computes) • propagation delay (computation takes time) • timing of signals is important (when does computation have its effect) • Data structures • size explicitly spelled out - no dynamic structures • no pointers • Parallelism • hardware is naturally parallel (must support multiple threads) • assignments can occur in parallel (not just sequentially) CSE 370 – Winter 2002 - Hardware Description Languages - 24

25. Hardware Description Languages and Combinational Logic • Modules - specification of inputs, outputs, bidirectional, and internal signals • Continuous assignment - a gate's output is a function of its inputs at all times (doesn't need to wait to be "called") • Propagation delay- concept of time and delay in input affecting gate output • Composition - connecting modules together with wires • Hierarchy - modules encapsulate functional blocks • Specification of don't care conditions CSE 370 – Winter 2002 - Hardware Description Languages - 25