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Introduction

Introduction. VHDL is used to: document circuits simulate circuits synthesize design descriptions Synthesis is the realization of design descriptions into circuits. In other words, it is the process by which logic circuits are created from design descriptions

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Introduction

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  1. Introduction • VHDL is used to: • document circuits • simulate circuits • synthesize design descriptions • Synthesis is the realization of design descriptions into circuits. In other words, it is the process by which logic circuits are created from design descriptions • This training course covers VHDL for PLD and CPLD synthesis • The course will at times draw upon the concepts of VHDL as a simulation language

  2. VHDL Design Descriptions • VHDL design descriptions consist of an ENTITY and ARCHITECTUREpair • The ENTITY describes the design I/O • The ARCHITECTURE describes the content of the design

  3. The Entity • A “BLACK BOX” • The ENTITY describes the periphery of the black box (the design I/O) BLACK_BOX rst q[7:0] d[7:0] co clk

  4. PORTS • The Entity (“BLACK BOX”) has PORTS • PORTS are points of communication • PORTS are often associated with the device pins or I/O’s of a component • PORTS are a special class of SIGNAL • PORTS have an associated SIGNAL name,MODE, and TYPE

  5. PORT modes A port’s MODE is the direction data is transferred: • IN Data that goes into the entity but not out • OUT Data that goes out of the entity but not in (and is not used internally) • INOUT Data that is bi-directional (goes into and out of the entity) • BUFFER Data that goes out of the entity and is also fed-back internally within the entity

  6. TYPES • VHDL is a strongly typed language (you cannot assign a signal of one type to the signal of another type) • BIT • a signal of type bit that can only take values of '0' or '1' • BIT_VECTOR • a grouping of bits (each bit can take value of '0' or '1') e.g., SIGNAL a: BIT_VECTOR (0 TO 3); -- e.g... ascending range SIGNAL b: BIT_VECTOR (3DOWNTO 0); -- e.g... descending range a <= "0111"; b <= "0101"; This means that: a(0) = '0' b(0) = '1' a(1) = '1' b(1) = '0' a(2) = '1' b(2) = '1' a(3) = '1' b(3) = '0'

  7. TYPES (contd.) • Warp recognizes two other signal types: • x01z • a signal bit that can take values ‘x’, ‘0’, ‘1’, or ‘z’ • this type is useful for three-state outputs and bi-directional signals • x01z_VECTOR • a grouping of x01z’s • assignment is similar to BIT_VECTOR

  8. TYPES (contd.) • INTEGER • useful as index holders for loops, constants, or generics • BOOLEAN • can take values ‘TRUE’ or ‘FALSE’ • ENUMERATED • has user-defined set of possible values example: TYPE states IS (start, slow, fast, stop); TYPE qit IS (‘0’, ‘1’, ‘z’, ‘x’);

  9. The Entity declaration • VHDL description of the black box: ENTITY black_box IS PORT ( clk, rst: INBIT; d: INBIT_VECTOR(7DOWNTO0); q: OUTBIT_VECTOR (7DOWNTO0); co: OUTBIT); END black_box; TYPE MODE BLACK_BOX rst q[7:0] d[7:0] co clk

  10. The Entity: An Example • Write an entity declaration for the following: Port D is a 12-bit bus, input only Port OE and CLK are each input bits Port AD is a 12-bit, bi-directional bus Port A is a 12-bit bus, output only Port INT is a three-state output Port AS is an output only my_design ad[11:0] d[11:0] a[11:0] oe int clk as

  11. The Entity: Example solution ENTITY my_design IS PORT ( d: IN BIT_VECTOR (11 DOWNTO 0); oe, clk: IN BIT; ad: INOUT x01z_VECTOR(11 DOWNTO 0); a: OUT BIT_VECTOR (11 DOWNTO 0); int: OUT x01z; as: OUTBIT); END my_design; my_design ad[11:0] d[11:0] a[11:0] oe int clk as

  12. Exercise #1: Entity Declaration • Write an entity declaration for the following: Port A is a 4-bit bus, input only Port EN, LD and CLK are input only Port W is an output only Port X is a 12-bit bi-directional bus Port Y is an output that is also used internally Port Z is a three-state output your_design en w ld x[11:0] clk y a[3:0] z

  13. Exercise #1: Solution ENTITY your_design IS PORT ( clk, ld, en: IN BIT; a: IN BIT_VECTOR(3DOWNTO0); w: OUT BIT; x: INOUT x01z_VECTOR(11 DOWNTO0); y: BUFFER BIT; z: OUT x01z); END your_design; your_design en w ld x[11:0] clk y a[3:0] z

  14. The Architecture • Architectures describe what is in the black box (i.e., the structure or behavior of entities) • Descriptions can be either a combination of • Structural descriptions • Instantiations (placements of logic gates - much like in a schematic - and their connections) of building blocks referred to as components • Behavioral descriptions • Abstract (or “high-level”) descriptions, e.g., IF a = b THEN state <= state5; • Boolean equations, e.g., x <= (a OR b) AND c;

  15. LOGIC a d b f c Entity/Architecture pairs • Since an architecture describes the behavior of an entity, they are paired together to form a design, e.g., ENTITY logic IS PORT ( a,b,c: IN BIT; f: OUT BIT); END logic; USE WORK.gatespkg.ALL; ARCHITECTURE archlogic OF logic IS SIGNAL d: BIT; BEGIN d <= a AND b; g1: nor2 PORT MAP (c, d, f); END archlogic; g1 Behavioral Structural

  16. Example Library Element (nor2) • Packages found in WARP\lib\common • nor2 in WARP\lib\common\gates.vhd -- gates.vhd Schematic support for synthesis. PACKAGE gatespkg IS ... COMPONENT NOR2 PORT( a,b : INBIT; qn : OUTBIT ); ENDCOMPONENT; ...

  17. Example Library Element (cont.) ... ENTITY NOR2 IS PORT( a,b : INBIT; qn : OUTBIT ); END NOR2; ARCHITECTURE archNOR2 OF NOR2 IS BEGIN qn <= (a NOR b); END archNOR2; ...

  18. Why use behavioral VHDL? • increased productivity, e.g., a 4-bit comparator a VHDL behavioral description: aeqb <= '1' WHEN a = b ELSE‘0’ ; a VHDL structural description: x1: xnor2 PORT MAP (a(0), b(0), xnr(0)); x2: xnor2 PORT MAP (a(1), b(1), xnr(1)); x3: xnor2 PORT MAP (a(2), b(2), xnr(2)); x4: xnor2 PORT MAP (a(3), b(3), xnr(3)); eq: or4 PORT MAP (xnr(0), xnr(1), xnr(2), xnr(3), aeqb); • increased portability, i.e., designs are not dependent on a library of vendor or device-specific components • more readable design flow

  19. Standard VHDL operators • Logical - defined for type BIT • AND, NAND • OR, NOR • XOR, XNOR • NOT • Relational - defined for types BIT, BIT_VECTOR, INTEGER • = (equal to) • /= (not equal to) • < (less than) • <= (less than or equal to) • > (greater than) • >= (greater than or equal to)

  20. Standard VHDL operators (contd.) • Unary Arithmetic - defined for type INTEGER • - (arithmetic negate) • Arithmetic - defined for type INTEGER • + (addition) • - (subtraction) • Concatenation - defined for types STRING, BIT, BIT_VECTOR • &

  21. Overloaded VHDL operators • Operators are defined to operate on data objects of specific types • For example, the ‘+’ operator is defined to operate on integers signal a,b,c : integer range 0 to 10; c <= a + b; • Operators can be “overloaded” to operate on data objects of other types • e.g., the ‘+’ operator may be overloaded to operate on bit_vectors and integers signal b,c : bit_vector(3 downto 0) ; c <= b + 2; • Warp provides a library to overload many operators

  22. VHDL semantics • There are two types of statements (The following is more easily understood in terms of simulation) • Sequential • Statements within a process are sequential statements and evaluate sequentially in terms of simulation • Concurrent • Statements outside of a process evaluate concurrently • Processes are evaluated concurrently (i.e., more than one process can be “active” at any given time, and all active processes are evaluated concurrently)

  23. Concurrent statements • Concurrent statements include: • boolean equations • conditional assignments (i.e., when...else...) • instantiations • Examples of concurrent statements: -- Two dashes indicates a comment in VHDL -- Examples of boolean equations x <= (a AND(NOT sel1)) OR (b AND sel1); g <= NOT (y AND sel2); -- Examples of conditional assignments y <= d WHEN (sel1 = '1') ELSE c; h <= '0' WHEN (x = '1' AND sel2 = '0') ELSE‘1’; -- Examples of instantiation inst: nand2 PORT MAP (h, g, f);

  24. Sequential statements: The Process • A process is a VHDL construct used for grouping sequential statements • Statements within a process are evaluated sequentially in terms of simulation • Processes can be either active or inactive (awake or asleep) • A Process typically has a SENSITIVITY LIST • When a signal in the sensitivity list changes value, the process becomes active • e.g., a process with a clock signal in its sensitivity list becomes active on changes of the clock signal

  25. The Process (contd.) • All signal assignments occur at the END PROCESS statement in terms of simulation time • The Process then becomes inactive

  26. s a(3 DOWNTO 0) x(3 DOWNTO 0) b(3 DOWNTO 0) Sequential statements: An Example • Example of sequential statements within a Process: mux: PROCESS (a, b, s) BEGIN IF s = '0' THEN x <= a; ELSE x <= b; END IF; END PROCESS mux; • Note: logic within a process can be registered or combinatorial • Note: the order of the signals in the sensitivity list is unimportant

  27. The Process Sensitivity List • A Process is invoked when one or more of the signals within the sensitivity list change, e.g., ARCHITECTURE archlist OF list IS BEGIN nand: PROCESS (a,b) BEGIN c <= NOT (a AND b); END PROCESS nand; END archlist; • Note: the process ‘nand’ is sensitive to signals ‘a’ and ‘b’ i.e., whenever signal ‘a’ or ‘b’ changes value, the statements inside of the process will be evaluated

  28. Signal Assignment in Processes ENTITY mux2ltch IS PORT ( a, b: INBIT_VECTOR(3 DOWNTO 0); s, en: INBIT; x: BUFFERBIT_VECTOR(3 DOWNTO 0)); END mux2ltch; s a(3 DOWNTO 0) x(3 DOWNTO 0) b(3 DOWNTO 0) en

  29. s a c x b en Desired Circuit Signal Assignment in Processes: Incorrect solution • Solution using a process with sequential statements: ARCHITECTURE archmux2ltch OF mux2ltch IS SIGNAL c: BIT_VECTOR (3DOWNTO 0); BEGIN mux: PROCESS (s, en) BEGIN IF s = '0' THEN c <= a; ELSE c <= b; END IF; x <= (x AND(NOT en)) OR (c AND en); END PROCESS mux; END archmux2ltch; • Note: when en, '1' =x is assigned the previous value of c

  30. END PROCESS: A correct solution • Solution using a process with sequential statements and a concurrent signal assignment: ARCHITECTURE archmux2ltch OF mux2ltch IS SIGNAL c: BIT_VECTOR (3 DOWNTO 0); BEGIN mux: PROCESS (s) BEGIN IF s = '0' THEN c <= a; ELSE c <= b; END IF; END PROCESS mux; x <= (x AND(NOT en)) OR (c AND en); END archmux2ltch; • Note: when en, '1' = x is assigned the updated value of c

  31. a(0 TO 3) aeqb b(0 TO 3) Exercise #2: Architecture Declaration of a Comparator • The entity declaration is as follows: ENTITY compare ISPORT( a, b: IN BIT_VECTOR (0 TO 3); aeqb: OUT BIT); END compare; • Write an architecture that causes aeqb to be asserted when a is equal to b • Multiple solutions exist

  32. Three possible solutions • Concurrent statement solution using a conditional assignment: ARCHITECTURE archcompare OF compare IS BEGIN aeqb <= '1' WHEN a = b ELSE ‘0‘; END archcompare; • Concurrent statement solution using boolean equations: ARCHITECTURE archcompare OF compare IS BEGIN aeqb <= NOT( (a(0) XOR b(0)) OR (a(1) XOR b(1)) OR (a(2) XOR b(2)) OR (a(3) XOR b(3))); END archcompare;

  33. a(0 TO 3) aeqb b(0 TO 3) Three possible solutions (contd.) • Solution using a process with sequential statements: ARCHITECTURE archcompare OF compare IS BEGIN comp: PROCESS (a, b) BEGIN IF a = b THEN aeqb <= '1'; ELSE aeqb <= '0'; END IF; END PROCESS comp; END archcompare;

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