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Characterization of Long Wire Data Leakage in Deep Submicron FPGAs

Characterization of Long Wire Data Leakage in Deep Submicron FPGAs. George Provelengios , Chethan Ramesh, Shivukumar B. Patil, Russell Tessier, Daniel Holcomb University of Massachusetts Amherst Ken Eguro Microsoft Research. Contribution.

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Characterization of Long Wire Data Leakage in Deep Submicron FPGAs

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  1. Characterization of Long Wire Data Leakage in Deep Submicron FPGAs George Provelengios, Chethan Ramesh, Shivukumar B. Patil, Russell Tessier, Daniel Holcomb University of Massachusetts Amherst Ken Eguro Microsoft Research

  2. Contribution • Quantifying FPGA channel wire coupling (new metric) • Recovering FPGA channel wire layout • Identifying channel wires prone to data leakage • Information leakage for channel wires on different FPGAs

  3. Accurately quantifying coupling – New metric

  4. Accurately quantifying coupling – New metric ∆RC = count diff. of logic ‘1’ and ‘0

  5. Accurately quantifying coupling – New metric • ∆RC = 2.66e-04 • ∆RC = 4.05e-04 (proposed metric) ∆RC depends on RO frequencies

  6. Accurately quantifying coupling – New metric ∆t = (proposed metric)

  7. Accurately quantifying coupling – New metric • ∆RC = 2.66e-04 • ∆t = 3.28ps • ∆RC = 4.05e-04 • ∆t = 3.32ps (proposed metric) ∆t captures only the change of the receiver delay

  8. Characterizing C4 wires for three different devices • The effect is present in three different technology nodes (60 to 20 nm) • ∆t/LAB: • CIV: 47.8 fs • S5GX: 14.0 fs • A10GX: 8.2 fs Measured values of ∆t versus length of C4 wire for Cyclone IV, Stratix V and Arria 10 devices

  9. Summary • A new metric for accurately quantifying coupling that exists between long wires • Able to measure delay changes on the order of femtoseconds • Using the proposed metric the channel layout can be inferred • Design isolation techniques for reducing data leakage risk can be devised • Characterizing coupling between different long wires types across three FPGA families: • Cyclone IV (60nm), Stratix V (28nm), and Arria 10 (20nm) • Come checkout my poster!

  10. Thank You

  11. Backup Slides

  12. Measured receiver frequency for different RO lengths • The two cases yield a similar value of ∆t but different values of the prior metric (∆RC)

  13. Adjacency map of a C4 channel in a CIV device • Characterizing coupling between wires allows inferring channel layout • Design isolation techniques could be used for protecting sensitive wires from eavesdropping Measured value of ∆t per C4 wire segment for all pairs of wires in C4 channel

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