INTRO TO VLSI DESIGN (CPE 448) (VHDL Tutorial )

1. INTRO TO VLSI DESIGN (CPE 448) (VHDL Tutorial) Prof: Asuif Mahmood

2. Files can be used to store data to be loaded into a model when it is run, or to store the results produced by simulation. • VHDL also provides specialized versions of file operations for working with text files. • VHDL provides sequential access to files using operations, such as “open”, “close”, “read” and “write”, that are familiar to users of conventional programming languages. • File Declarations: • file identifier { ,… }: subtype_indication • [[ open file_open_kind_expression ] is string_expression] FILES and INPUT/OUTPUT

3. If a file is opened in a read mode, successive elements of data are read from the file using the read operation. • Reading starts from the first element in the file, and each time an element is read the file position advances to the next element. • We can use the endfile operation to determine when we have read the last element in the file. Syntax: type file_type is file of element_type; read and endfile operations are implicitly declared as procedure read ( file f : file_type; value : out element_type); function endfile ( file f : file_type) return boolean; Reading from Files

4. Library ieee; • Use ieee.std_logic_1164.all; • entity ROM is • generic (load_file_name : string); • port( sel : in std_logic; • address : in std_logic_vector; • data : in std_logic_vector); • end entity ROM; • architecture behavioral of ROM is • begin • behavior : process is • subtype word is std_logic_vector( o to data’length – 1); • type storage_array is array (natural range 0 to 2**address’length –1 ) of word; • variable storage : storage_array; • variable index : natural; • --other declarations • type load_file_type is file of word; • file load_file: load_file_type open read_mode is load_file_name; • begin • --load ROM contents from load_file • index := 0; • while not endfile (load_file) loop • read ( load_file, storage(index)); • index := index + 1; • end loop; • --respond to ROM accesses • loop • --- other instructions • end loop; • end process behavior; • end architecture behavioral; Reading from Files (Example)

5. If a file is open in write mode, a new empty file is created in the host computer’s file system, and successive data elements are added using the write operation. • implicitly declared as procedure write ( file f : file_type; value : in element_type); Writing to Files

6. architecture instrumented of CPU is • type count_file is file of natural; • file instruction_counts: count_file open write_mode is “instructions”; • begin • interpreter : process is • variable IR : word; • alias opcode : byte is IR(0 to 7); • variable IR : word; • type counter_array is • array (0 to 2**address’length –1 ) of natural; • variable counters : counter_array:=(others =>0); • begin • --initialize the instruction set interpreter • instruction_loop: loop • --fetch the next instruction into IR • --decode the instruction • opcode_number := convert_to_natural(opcode); • counters(opcode_number) := counters(opcode_number)+1; • -- execute the decoded instruction • case opcode is • when halt_opcode => exit instruction_loop; • end case; • end loop instruction_loop; • for index in counters’range loop • write (instruction_counts, counters(index)); • end loop; • wait; -- program finished, wait forever • end process interpreter; • end architecture instrumented; Writing to Files (Example)

7. The concept of type is very important when describing data in a VHDL model. • The type of a data object defines the set of values that the object defines the set of values that the object can assume, as well as the set of operations that can be performed on those values. • A scalar type consists of single, indivisible values. Scalar Data Types and Operations

8. Both constants and variables need to be declared before they can be used in a model. • A declaration simply introduces the name of the object, defines its type and may give it an initial value. constantnumber_of_bytes : integer := 4; constantnumber_of_bits : integer := 8*number_of_bytes; constante : real := 2.718281828; constantprop_delay : time := 3 ns; variable index: integer := 0; variable start, finish : time := 0 ns; CONSTANTS and VARIABLES

9. Example: • One restriction on where a variable declaration may occur is that it may not be placed so that the variable would be accessible to more than one process. • The exception to this rule is if a variable is declared specially as shared variable. architecturesample ofent is constantpi : real : 3.14159 begin processis variablecounter : integer; begin --do anything endprocess; endarchitecturesample; CONSTANTS and VARIABLES (cont.)

10. A scalar type is one whose value are indivisible. • typeapples is range 0 to 100; • typeoranges is range 0 to 100; packageint_types is typesmall_int isrange0 to255; end packageint_types; usework.int_types.all; entitysmaller_adder is port( a, b : in small_int; s : out small_int); end entitysmall_adder; SCALAR TYPES

11. A predefined type integer is included, which includes all whole numbers representable on a particular host computer. typeday_of_month is range0 to31; typeyear is range0 to2100; variable today: day_of_month := 19; variable start_year: year := 2002; **It is illegal to make the assignment: start_year := today; INTEGER TYPES

12. typeINPUT_LEVEL is range–10.0 to10.0; typeprobability is range0.0 to1.0; variable input_A: input_level; FLOATING-POINT TYPES

13. Examples: typeresistance is range0 to1E9 units ohm; kohm = 1000ohm; Mohm = 1000kohm; end unitsresistance; **We can use them as 5 ohm 22 ohm 4kohm typetime is rangeimplementation defined units fs; ps=1000fs; ns=1000ps; us=1000ns; ms=1000us; sec=1000ms; min=60sec; hr=60min; end unitstime; PHYSICAL TYPES

14. typealu_function is (disable, pass, add, subtract, multiply, divide); typeoctal_digit is ( ‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’‘,7’); variable alu_op: alu_function; variable last_digit: octal_digit := ‘0’; and make assignments to them: alu_op := subtract; last_digit := ‘7’; ENUMERATION TYPES

15. When we write complex behavioral models it is useful to divide the code into sections, each dealing with a relatively self-contained part of the behavior. • There are two kinds of subprograms: procedures and functions. • Procedure encapsulates a collection of sequential statements that are executed for their effect . • Function encapsulates a collection of statements that compute a result. • Thus a procedure is a generalization of a statement, whereas a function is a generalization of an expression. Subprograms

16. There are two aspects to using procedures in a model: • First the procedure is declared . • Then elsewhere the procedure is called. procedure identifier [ (parameter_interface_list) ] is { subprogram_declarative_part } begin { sequential_statement } endprocedure [ identifier ]; PROCEDURES

17. procedureaddu ( a, b : in word32; result : out word32; overflow : out Boolean ) is variable sum: word32; variable carry: bit := ‘0’; begin for index in sum’reverse_range loop sum(index):=a(index) xor b(index) xor carry; carry:=(a(index) and b(index) ) or (carry and (a(index) xor b(index) ) ); end loop; result:=sum; overflow:=carry = ‘1’; end procedureaddu; **A call to this procedure may appear as follows: variable PC, next_PC: word32; variable overflow_flag: boolean; addu ( PC, X”0000_0004”,next_PC, overflow_flag); PROCEDURES (Example)

18. The syntax rule for a function declaration is very similar to that for a procedure declaration: function identifier [ (parameter_interface_list) ] return type_mark is { subprogram_declarative_part } begin { sequential_statement } endfunction [ identifier ]; FUNCTIONS

19. functionlimit ( value, min, max : integer) returninteger is begin if value > max then return max; elsif value < min then return min; else return value; endif; end function limit; • Call to this function might be included in a variable assignment statement, as follows: new_temperature := limit ( current_temperature + increment, 10,100); FUNCTIONS

20. A VHDL package is simply a way of grouping a collection of related declarations that serve a common purpose. • They might be a set of subprograms that provide operations on a particular type of data . • Or they might just be the set of declarations needed to model a particular design. • The important thing is that they can be collected together into a separate design unit that can be worked on independently and reused in different parts of a model. package identifier is { package_declarative_item } begin { sequential_statement } endpackage [ identifier ]; Package

21. package cpu_types is constant word_size : positive := 16; constant address_size : positive := 24; subtype word is bit_vector(word_size-1 downto 0); subtype address is bit_vector(address_size-1 downto 0); type status_value is (halted, idle, fetch, mem_read, read, mem_write, io_read, io_write, int_ack); subtype opcode is bit_vector(5 downto 0); function extract_opcode (instr_word: word) return opcode; constant op_nop : opcode := “000000”; constant op_breq : opcode:= “000001”; constant op_brne : opcode:= “000010”; constant op_add : opcode := “000011”; end package cpu_types; Package (Example)

22. entity address_decoder is port ( addr: in work.cpu_type.address; status: in work.cpu_type.status_value; mem_sel, int_sel, io_sel : out bit); end entity address_decoder; architecture behavioral of cpu is -- define constant mem_low: work.cpu_type.address:=X”000000”; begin interpreter : process is variable instr_reg :work.cpu_types.word; variable instr_opcode : work.cpu_types.opcode; begin -- initialize loop -- fetch instruction instr_opcode:= work.cpu_types.extract_opcode( instr_reg): case instr_opcode is when work.cpu_types.op_nop => null; when work.cpu_types.op_breq => null; end case; end loop; end process interpreter; end architecture behavioral; Package (Example)