ECE 448 FPGA and ASIC Design with VHDL

1. ECE 448 FPGA and ASIC Design with VHDL Spring 2010

2. ECE 448 Team Course Instructor:Kris Gaj kgaj@gmu.edu Lab Instructors (TAs): Monday & Tuesday section: Jeremy Kelly jeremy.a.kelly (at) gmail.com Wednesday section: John Phamjhnphm (at) gmail.com Thursday section: Brian Loopbdloop (at) gmail.com

3. ECE 448 Team – Division of Tasks Course Instructor – Primary Responsibilities • Lectures • Preparing and grading exams and quizzes • - Coordination of work on development • of new experiments • Instructions for the lab experiments • Coordination of work done by the TAs • Enforcing consistent policies and grading standards • Mid-semester student satisfaction survey • Resolving conflicts and providing feedback to the TAs • Holding office hours

4. ECE 448 Team – Division of Tasks Lab Instructors (TAs) – Primary Responsibilities • Teaching hands-on sessions on how to use software, hardware and testing equipment needed for experiments • Introductions to the lab experiments • Grading student demonstrations and reports • Holding office hours • Development and testing of new lab experiments

5. ECE 448 Section Assignment Rules • You are welcome to attend any of the • multiple office hour sessions • Please attend the class meetings of the other section only • in case of emergency and give preference in access • to the lab computers to the students attending • their own section • All experiment demonstrations need to be done • in the presence of your TA, and can be • done exclusively during the class time of your section

6. Course Hours Lecture: Monday, Wednesday 5:55-7:10 PM, Lecture Hall, room 2 Lab Sessions: Monday, Tuesday, Wednesday, Thursday 7:20-10:00 PM, The Nguyen Engineering Bldg., room 3208 There will be no lab meetings in the first week of classes!!!

7. Tentative Office Hours Saturday, 12:00-1:00 PM, John Pham, Engineering 3208 Monday, 7:30-8:30 PM, Kris Gaj, Engineering 3225 Monday, 10:00-11:00 PM, Jeremy Kelly, Engineering 3208 Tuesday, 6:00-7:10 PM, Jeremy Kelly, Engineering 3208 Wednesday, 4:30-5:30 PM, Kris Gaj, Engineering 3225 Wednesday, 7:30-8:30 PM, Brian Loop, Engineering 3204

8. Lab Access Rules and Behavior Code Please refer to Computer Engineering Lab website and in particular to Access rules & behavior code

9. Grading criteria First part of the semester (before the Spring break) Lab experiments - Part I 20% Quizzes & homework: 5% Midterm exam for the lecture: 10% Midterm exam for the lab: 15% Second part of the semester (after the Spring break) Lab experiments - Part II    20% Quizzes & homework: 5% Final exam 25%

10. Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience, 2008. Required Textbook Recommended Textbook current ECE 331/332 book Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 3rd or 2nd Edition

11. Undergraduate Computer Engineering Courses ECE 331 ECE 332 CS 112  C  C  C ECE 445  C  C CS 211 ECE 448  C  C CS 222 ECE 447 ECE 492 CS 262  C ECE 493 Color code: BS EE CS 367 BS CpE

14. ECE 448, FPGA and ASIC Design with VHDL Topics VHDL: - writing synthesizable RTL level code in VHDL - writing test benches FPGAs: - architecture of FPGA devices - tools for the computer-aided design with FPGAs - current FPGA families & future trends

15. High-level ASIC Design: - standard cell implementation approach - logic synthesis tools - differences between FPGA & standard-cell ASIC design flow Applications: - basics of computer arithmetic - applications from communications, cryptography, digital signal processing, bioengineering, etc. Platforms: • FPGA boards • microprocessor board–FPGA board interfaces • reconfigurable computers New trends: • using high-level programming languages to design hardware • microprocessors embedded in FPGAs

16. Tasks of the course Comprehensive introduction to FPGA & front-end ASIC technology Advanced course on digital system design with VHDL Testing equipment • hardware: • Xilinx FPGAs, • Library of standard ASIC cells • software: • VHDL simulators • Synthesis tools • Xilinx ISE • writing VHDL code • for synthesis • design using • finite state machines • and algorithmic state • machines • testbenches - oscilloscopes - logic analyzer

17. VHDL for Specification VHDL for Simulation VHDL for Synthesis

18. Levels of design description Algorithmic level Level of description most suitable for synthesis Register Transfer Level Logic (gate) level Circuit (transistor) level Physical (layout) level

19. Combinational Logic Combinational Logic Register Transfer Level (RTL) Design Description … Registers

20. dataflow VHDL Design Styles VHDL Design Styles • Testbenches structural behavioral Components and interconnects Concurrent statements Sequential statements • Registers, counters, etc. • State machines Subset most suitable for synthesis

21. Testbench Environment TB Processes Generating Stimuli Design Under Test (DUT) Testbenches Stimuli All DUT Inputs Simulated Outputs

22. World of Integrated Circuits Integrated Circuits Full-Custom ASICs Semi-Custom ASICs User Programmable PLD FPGA PAL PLA PML LUT (Look-Up Table) MUX Gates

23. Block RAMs Block RAMs What is an FPGA? Configurable Logic Blocks I/O Blocks Block RAMs

24. Two competing implementation approaches FPGA FieldProgrammable GateArray ASIC ApplicationSpecific IntegratedCircuit • designed all the way • from behavioral description • to physical layout • no physical layout design; • design ends with • a bitstream used • to configure a device • designs must be sent • for expensive and time • consuming fabrication • in semiconductor foundry • bought off the shelf • and reconfigured by • designers themselves

25. FPGAs vs. ASICs FPGAs ASICs Off-the-shelf High performance Low development costs Low power Short time to the market Low cost (but only in high volumes) Reconfigurability

26. FPGA Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Specification (Lab Experiments) On-paper hardware design (Block diagram & ASM chart) VHDL description (Your Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31downto0); data_output: out std_logic_vector(31downto0); out_full: in std_logic; key_input: in std_logic_vector(31downto0); key_read: out std_logic; ); end AES_core; Functional simulation Synthesis Post-synthesis simulation

27. FPGA Design process (2) Implementation Timing simulation Configuration On chip testing

28. Simulation Tools

31. FPGA Synthesis Tools

32. Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW;

33. After synthesis the entire implementation process is performed by FPGA vendor tools FPGA Implementation

35. Design Process control from Active-HDL

36. Top Level ASIC Digital Design Flow Design Inception RTL Design Synthesis Macro Development Place + Route Physical Verification Design Complete

37. ASIC Simulation Tools

38. ASIC Synthesis Tools

39. Xilinx FPGA Tools Windows ECE Labs Home ModelSim Xilinx Edition Aldec Active HDL Student Edition Aldec Active HDL Synopsys Synplify Pro Xilinx XST Xilinx ISE Xilinx XST (limited) Xilinx WebPACK (limited) Xilinx XST (limited) Xilinx WebPACK (limited)

40. Digilent Basys2 FPGA Board

41. Digilent Basys2 FPGA Board

42. FPGA available on the board Xilinx Spartan 3E-100,XC3S100E FPGA • 100,000 equivalent logic • gates • 960 CLB slices • 72 kbits of memory in block RAMs Block RAMs Programmable Interconnects Configurable Logic Block slices (CLB slices)

44. Digital system design technologies coverage in the CpE & EE programs at GMU ASICs Microprocessors FPGAs Computer Organization ECE 445 ECE 447 ECE 431 Digital Circuit Design Single Chip Microcomputers ECE 448 FPGA and ASIC Design with VHDL ECE 545 Digital System Design with VHDL ECE 511ECE 611 ECE 645 Microprocessors Computer Arithmetic Digital Integrated Circuits Advanced Microprocessors ECE 586 ECE 681 VLSI Design for ASICs

45. Why ECE 448 is a challenging course? • need to “relearn” VHDL • need to learn new tools • need to perform practical experiments • time needed to complete experiments

46. ECE 448: Spring 2006 Student Survey Summary

47. Difficulties • finding time to do the labs - 15 • learning VHDL – 2 • getting used to software – 1

48. Average time spent per one experiment 9 8 7 6 5 4 3 2 1 0 2 6 8 10 15 20 24 30 32 48

49. Self-evaluation 3 – better than expected 8 – worse than expected 16 – as well as expected

50. Why is this course worth taking? • VHDL for synthesis: • one of the most sought-after skills • knowledge of state-of-the-art tools used in the industry • knowledge of the modern FPGA & ASIC technologies • knowledge of state-of-the-art testing equipment • design portfolio that can be used during job interviews • unique knowledge and practical skills that make you • competitive on the job market