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FPGA VHDL eP32 Design

FPGA VHDL eP32 Design. 2012 FIG Taiwan Conference February 17, 2012 Chen-Hanson Ting. Summary. Brevia FPGA Development Kit Architecture of eP32 Implementing eP32 Memory and IO Brevia Board and LatticeXP2 ispLEVEL and Diamond IDE Demomnstration. Brevia FPGA Development Kit.

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FPGA VHDL eP32 Design

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  1. FPGA VHDL eP32 Design 2012 FIG Taiwan Conference February 17, 2012 Chen-Hanson Ting

  2. Summary • Brevia FPGA Development Kit • Architecture of eP32 • Implementing eP32 • Memory and IO • Brevia Board and LatticeXP2 • ispLEVEL and Diamond IDE • Demomnstration

  3. Brevia FPGA Development Kit • Lattice XP2 Brevia Kit is a complete FPGA development system for $49. • The FPGA chip on Lattice Brevia Kit let us design and implement your own microcontrollers. • A 32-bit Forth microcontroller eP32 is demonstrated here.

  4. Brevia FPGA Development Kit • For $49, you can design, build and test your own microcontroller. • The on-board FPGA chip, LatticeXP5E, can host a complete 32-bit microcontroller system. • eP32 is implemented in VHDL, with Forth operating system and programming language.

  5. LatticeXP2 Brevia Kit

  6. Brevia Board • LatticeXP2-5E 6TN144C FPGA • 2-Mbit SPI flash memory • 128K by 8-bit SRAM • 8 switches/pushbuttons • 8 status LEDs • USB download and serial cable

  7. LatticeXP2-5E 6TN144C • 5K LUT4 Logic cells • 166K Bits Embedded block memory • 10K Bits Distributed memory • 3 DSP Blocks • 12 18x18 Multipliers • 144 Pin TQFP Package

  8. The Most Satisfying FPGA • I have tried FPGA’s from all Big 4: • Market Share 2009 Sales FPGA • Xilinx 50% $1,825M Virtex, Spartan • Altera 30% $360M Stratix, Cyclone • Lattice 10% $194M ECP3, XP2 • Actel 6% $190M IGLOO, ProASI • Lattice has the most satisfying FPGA, a single chip SOC solution • Lattice has the cheapest development board. $49 • Lattice provides free development software.

  9. Brevia Design Tools • ispLEVEL or DIAMOND IDE • Synthesis: Synplify • Simulation: Active-HDL from Aldec • Layout: Design Planner • Flash Programming: ispVMR • Tracing and Debugging: ispReveal

  10. Architecture of eP32 • A 32-bit CPU (Central Processing Unit) • Two stacks to support Forth Language: • Return stack for nested return addresses • Parameter stack to pass parameters among nested subroutines • Minimal instruction set • Single clock cycle execution time • Optimized subroutine call and return

  11. Block Diagram of eP32 CPU

  12. ALU and Data Processing Unit

  13. Program and Data Memory Unit

  14. Return Address Processing Unit

  15. Instruction Execution Unit

  16. Instruction Execution Timing

  17. Instruction Set of eP32 CPU • Minimum Instruction Set Computer (MISC) • Only 27 Instructions, expandable to 64 instructions • 4 Types of instructions: • Program transfer instructions • Memory access instructions • ALU instructions • Register and stack instructions

  18. Program Transfer Instructions • BRA Branch always • RET Return from subroutine • BZ Branch on zero • BC Branch on carry • CALL Call subroutine • NEXT Loop until R is 0

  19. Memory Access Instructions • LDX Load from memory • LDXP Load from memory and increment X register • LDI Load immediate value • STX Store to memory • STXP Store to memory and increment X register

  20. ALU Instructions • ADD Add S to T • AND AND S to T • XOR XOR S to T • COM One’s Complement of T • SHR Shift T to right • SHL Shift T to left • RR8 Rotate T right by 8 bits • MUL Multiplication step • DIV Division step

  21. Register and Stack Instructions • DUP Duplicate T to S • DROP Pop S to T • PUSH Push T to R • POP Pop R to T • OVER Duplicate S over T • TX Load X to T • XT Store T to X • NOP No operation

  22. Implementing eP32 • eP32_chip.vhd, top level design • eP32q_tb.vhd, test bench • Modules • eP32.vhd, CPU core • Ram_memory.vhd, 4096x32 auto-initialized RAM memory • Uart.vhd, 115200 baud • Gpio.vhd, 16 bit bidirectional

  23. Synthesizing eP32 • Ep32.vhd, uart.vhd and gpio.vhd are synthesized without modification • Ram_memory.vhd must be constructed to use RAM_Q modules in LatticeXP2-5E FPGA chip. • Ep32_chip.vhd instantiates new ram_memory.vhd with all other modules

  24. Simulating eP32 • Active-HDL simulation tools are supplied by Aldec. • ispLEVEL needs a test bench module for functional simulation of eP32 chip: ep32q_tb.vhd • DIMOND simulates ep32_chip directly.

  25. Memory and IO • Design Planner to assign following signals to physical pins: • External reset • External master clock • Interrupts • GPIO to LED and switches • UART transmit • UART receiver

  26. Programming XP25E FPGA • Connect USB cable to PC. • Invoke Programmer to download ep32_xp2.jed file. • eP32 eForth boots up and sends sign-on message to HyperTerminal console.

  27. Demonstration • Boot up eForth on eP32. • Universal greeting “Hello, World!”. • Turn LED’s on and off. • Read switches and push buttons.

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