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Status of the CBM ToF TDC Development

Status of the CBM ToF TDC Development. Detector Requirements TDC Core & Testchip Performance Architecture & Readout Concept Status and Submission Plans. Detector Requirements. Time Resolution < 25 ps Double Hit Resolution < 10 ns (better < 5 ns) Time over Threshold Yes

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Status of the CBM ToF TDC Development

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  1. Status of the CBM ToF TDC Development • Detector Requirements • TDC Core & Testchip Performance • Architecture & Readout Concept • Status and Submission Plans

  2. Detector Requirements • Time Resolution < 25 ps • Double Hit Resolution < 10 ns (better < 5 ns) • Time over Threshold Yes • Power Consumption < 60 mW / Ch • Integration Level min. 4 Ch / Chip

  3. Status of the CBM ToF TDC Development • Detector Requirements • TDC Core & Testchip Performance • Architecture & Readout Concept • Status and Submission Plans

  4. DLL based TDC Core • Delay Locked Loop Closed regulation loop with a chain of N identical elements with adjustable delay, Phase Detector, Charge Pump and Loop Filter • + Good resolution • + Self calibration • + Dead time free operation • + Low power consumption

  5. Chip submitted in Feb 2007 Testchip DANTE DLL • DLL structure with 64 DE • 160MHz clock input • Intrinsic bin size: ~ 50ps • Additional components: Hit-Reg, RO-Logic • 1 Bit serial output • Size: 1525µm x 1525µm Phase Detector Charge Pump Loop Filter 870µm 210µm Ref Clk Delay Chain

  6. DANTE DoubleBin DLL • Power consumption DLL (Sim.) I = 3 mA @1.8V => 5.4 mW • Power consumption DANTE (Mea.) • I = 18 mA @1.8V • => 32.4 mW • Resolution • σuc = 20.34 ps ± 0.15ps • DNL: (+ 0.34 / - 0.38) LSB • INL: (+ 0.51 / - 0.49) LSB

  7. Status of the CBM ToF TDC Development • Detector Requirements • TDC Core & Testchip Performance • Architecture & Readout Concept • Status and Submission Plans

  8. Architecture & Readout Concept • 4 Channels with LVDS Input • 2 Events / Clock Cycle → Double Hit Resolution: ≤ 3.1 ns • Time over Threshold Measurement • Serial Data Communication

  9. Timing and Synchronisation • CBM System Clock : 250 MHz ( TSys = 4 ns ) • DLL Clock: 156.25 MHz ( = 5/8 * 250 MHz ) • Intrinsic Time Binning : 50 ps • 12 Bit Timestamp Counter • TEpoche = 26.2144 µs • For Synchronisation: 2048 * TSys = 5 * TEpoche • Synchronisation Intervall : TSync = 131.072 µs

  10. Readout Concept for TDC Chips Readout structure exists in VHDL and is under test TDC Core Fine Time 7bit Time Stamp 12bit Channel # 2bit L/F-Edge 1bit Chip ID 8bit Extension 2bit Clock

  11. Status of the CBM ToF TDC Development • Detector Requirements • TDC Core & Testchip Performance • Architecture & Readout Concept • Status and Submission Plans

  12. Status and Submission Plans • Schematic and Layout for Time Core • Parasitic Simulation still missing • Design of Readout Logic • Submission planed for summer 2008

  13. Thank you for your attention

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