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SRAM

SRAM. Mohammad Sharifkhani. Effect of Mismatch. Data Retention Voltage. DRV Mote-carlo simulation. Inv. with VL Input @ Read load. Init cond. VL=1, VH=0. Inv. with VR Input @ Write load. Shmoo plot.

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SRAM

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  1. SRAM Mohammad Sharifkhani

  2. Effect of Mismatch

  3. Data Retention Voltage

  4. DRV Mote-carlo simulation

  5. Inv. with VL Input @ Read load Init cond. VL=1, VH=0 Inv. with VR Input @ Write load

  6. Shmoo plot • A shmoo plot is a graph that represents how a particular test passes or fails when parameters like frequency, voltage, or temperature are varied and the test is executed repeatedly. • The shape of the failing region is meaningful and helps in determining the cause of the failure. • A shmoo plot of normal circuit operation shows better high-frequency performance as supply voltage increases, as shown in Fig. 1a. • Other shapes frequently seen include the curlback (Fig. 1b), ceiling (Fig. 1c), floor (Fig. 1d), wall (Fig. 1e), finger (Fig. 1f), and breaking wave (Fig. 1g).

  7. Techniques for improving reliability • Read assist circuits • Write assist circuits • Error correction methods

  8. Multiple voltages for NM improvement

  9. Threshold voltage variation Monte-carlo simulation Access (reduction in the BL-differential produced), Higher Vt  lower BL swing Read (data flipping while reading), lower v-trip write (unsuccessful write) Higher Vt  weaker PU ration hold (data flipping at a lower supply voltage in standby mode) S. Mukhopadhyay, JSSC 2007

  10. Solution: Adaptive body bias

  11. Dynamic VDD Selection Higher write noise margin  more power

  12. Read Write-assist circuits Keeps WL voltage in check (lower for stable read) Charge redistribution between cell VDD and down Vdd

  13. Pulsed WL and BL Minimization of WL activation Threats write: Read Modify Write is used for all columns

  14. Pulsed WL and BL On pseudo read columns the BLs are precharged to a lower voltage than VDD to maintain stability of the cell  Weaker access  lower delta V to trip the cell

  15. Dynamic Body Bias On-chip programmable voltage generator with N-well resistors Forward BB: stronger PMOS makes a wider butter fly curve more SNM during read operation Higher leakage (only applied on selected banks)

  16. Read assist Local SA Pilo, JSSC’07 Divided BLs

  17. Read assist When enabled the half selected BL/read BL get full swing Masks the BL of the half selected columns that do not need full amplification to save power 10% more power at nominal voltage Yet allows for 1.20.9 VDD reduction and keeps the array stable  saves power at the end Mask registers are loaded during power up

  18. Write assist Weaker PMOS is needed Supply reduction of the to be written cells by ~200mV Only the columns to be written on get the lower supply voltage: a power decoder is needed

  19. Reference generator Bi-directional/data dependent current flow Write voltage Old data: VDDVWR New data: sink data from VWR to charge up the new 1 node Writing old data pulls up VWR  push-pull is needed at Ref. Generator

  20. Redundancy in SRAMs

  21. Redundancy

  22. Error Correction Code

  23. Multi-bit errors

  24. Multi-bit errors: Interleaving

  25. Future trends • More than 6T cells • Change in technology • eDRAM

  26. More transistors

  27. Thin Body MOSFETs

  28. Double Gate FinFET

  29. Double Gate vs. Tri-Gate

  30. Independent Gate operation

  31. Applications

  32. Independent Gate Operation6-T SRAM in Bulk-Si

  33. 6T SRAM with FinFET

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