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Computer Organization Lecture 19

Computer Organization Lecture 19. Exam 2 results Project 4: Memory Microprogramming: R-type. Exam 2 statistics. From Lecture 12 & 17. MIPS controller. Outputs. Outputs. Inputs IR(31:25). Outputs. Inputs. NS Decoder. Output Decoder. Present State. Flip Flops. Combo logic.  ROM.

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Computer Organization Lecture 19

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  1. Computer OrganizationLecture 19 Exam 2 results Project 4: Memory Microprogramming: R-type University of Portland School of Engineering

  2. Exam 2 statistics University of Portland School of Engineering

  3. From Lecture 12 & 17 MIPS controller Outputs Outputs Inputs IR(31:25) University of Portland School of Engineering

  4. Outputs Inputs NS Decoder Output Decoder Present State Flip Flops Combo logic ROM FSM architecture University of Portland School of Engineering

  5. Project 5: Memory • Memory contains ROM and RAM • Size: 16K words • ROM: first 256 words • RAM: remaining 16K words • Not installed: 17K – 64K words • Due: Wednesday, November 17 University of Portland School of Engineering

  6. Requirements Address Map Inputs Outputs University of Portland School of Engineering

  7. MicroAsm • Java application: MicroAsm.class, SavitchIn.class • Microinstruction: free format, no fixed fields • Requires input file: text-only, file.upg • Creates output file: file.txt • Errors: command line file name,file I/O, unrecognizable token • Execution: BlueJ or DOS command line University of Portland School of Engineering

  8. uProgram tokens University of Portland School of Engineering

  9. uProgram tokens, continued. University of Portland School of Engineering

  10. uProgram tokens, continued. University of Portland School of Engineering

  11. ID IF Reset 2 clocks sll srl lw sw R-fmt nop 1- 3 additional clocks j beq addi subi andi ori MDP16 state diagram University of Portland School of Engineering

  12. Alua-pc Alub-ext imm aluopadd branch IRWr PCinc IF/ID states • Write instruction from memory into IR, Increment the program counter (clock 1) • Determine optimistic branch address Dispatch to opcode (clock 2) University of Portland School of Engineering

  13. R-type microprogram • Func bits (IR[3:0]) determine ALU operation (clock 3) • Write result into register file (clock 4) Rwr reg_Ralu Return aluA_R0 aluB_R1 University of Portland School of Engineering

  14. R-type microprogram University of Portland School of Engineering

  15. ID IF Reset sll srl lw sw R-fmt nop j beq addi subi andi ori MDP16 state diagram University of Portland School of Engineering

  16. Sll instruction • ALU function is shift left logically • Write result into register file University of Portland School of Engineering

  17. Sll EX state? • Origin: 0x20 • Operation: clock 3 • RALUout = A << 1 • Functional units • uPgm must control ALU function • ALU funct = shift left logically • ALU input • R0 University of Portland School of Engineering

  18. Sll WB state? • Next: return to IF • Operation: clock 4 • Reg [ IR(10)] = ALUout • Functional units • Must write to reg file • Data comes from RALU • Use IR[10] as destination register University of Portland School of Engineering

  19. ID IF Reset sll srl lw sw R-fmt nop j beq addi subi andi ori MDP16 state diagram University of Portland School of Engineering

  20. Store instruction • Find the effective address • Write register contents to memory University of Portland School of Engineering

  21. Store EX state? • Origin: 0x50 • Operation: clock 3 • ALUout = A + sign-extend (IR[0:9]) • Functional units • uPgm must control ALU function • ALU funct = add • ALU inputs • R0 • Sign-extended offset University of Portland School of Engineering

  22. Store MEM state? • Next: return to IF • Operation: clock 4 • Memory [ALUout] = B • Functional units • RALU addresses memory • R1 written into memory University of Portland School of Engineering

  23. Completed Microcode ROM University of Portland School of Engineering

  24. University of Portland School of Engineering

  25. Sll microprogram • ALU function is shift left logically (clock 3) • Write result into register file (clock 4) Rwr reg_Ralu regFmt Return Imm aluA_R0 aluOpSll University of Portland School of Engineering

  26. Sll microprogram University of Portland School of Engineering

  27. Store microprogram • Find the effective address (clock 3) • Write register contents to memory (clock 4) Imm aluA_R0 aluB_ext aluOpAdd IoD MemWr return University of Portland School of Engineering

  28. Store microprogram University of Portland School of Engineering

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