Design TWG

1. Design TWG 2000 Update Plans for 2001 Hsinchu, Taiwan December 2000

2. Role of Design in ITRS • Before 1999 • Focused on hardware design and test: tool issues and technologies • Detached from rest of Roadmap • 1999 • Highlighted SOC trends and requirements • Better integration, interaction with other ITWGs • 2001 and beyond • Much more involvement in crosscut issues with other ITWGs • E.g., panel on interconnect systems and optimization; chip size; cost; ... • Bidirectional interactions with other ITWGs • Consideration of new and important areas: • Applications • Architectures • Optimized uses of process technology • Analog/mixed signal and other technologies • More quantitative data/metrics/cost issues

3. 1 K 1 Billion # Transistors Superexponential Design Complexity Functionality + Testability Functionality + Testability + Wire Delay Functionality + Testability + Wire Delay + Power Mgmt Functionality + Testability + Wire Delay + Power Mgmt +Embedded software Functionality + Testability + Wire Delay + Power Mgmt +Embedded software +Signal Integrity Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips + RF Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips + RF + Packaging Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips + RF + Packaging + Mgmt of Physical Limits • Exponentially growing number of devices • Design complexity is exponential function of device count

4. 3 Yr. Design YearTechnologyChip Complexity FrequencyStaffStaff Cost* 250 nm 250 nm 180 nm 130 nm 13 M Tr. 20 M Tr. 32 M Tr. 130 M Tr. 400 500 600 800 210 270 360 800 90 M 120 M 160 M 360 M 1997 1998 1999 2002 Design Productivity Crisis Potential Design Complexity and Designer Productivity 10,000 100,000 100,000,000 Equivalent Added Complexity Logic Tr./Chip 10,000 1,000 1,000,000 Tr./S.M. Productivity (K) Trans./Staff - Mo. 100 1,000 100,000 58%/Yr. compounded Complexity growth rate 10 100 Logic Transistor per Chip (M) 10,000 100,000 1 10 1,000 10,000 x x 1 0.1 100 x x 21%/Yr. compound Productivity growth rate x x x x 0.1 0.01 10 100 0.01 0.001 1 10 1983 1985 1987 1989 1991 1995 1997 1999 2001 2003 2005 2009 2007 1981 1993 * @ $150K / Staff Yr. (In 1997 Dollars)

7. The Need for Built-In Self-Test • Chip boundary cannot support needed data volumes without increasing test time (20x - 100x!!)

8. Model for SOC Design(a reasonable scenario) • Design effort = constant (small design team, short time to product) • New design productivity (logic) : + 30%/yr • (Reuse design productivity) = (New design productivity) / 2 • Chip size is up to 1 cm2 • Result: up to 94 % of die occupied by memory, or smaller die

9. A Scenario for SoC Design Productivity

10. A Scenario for SoC Design Productivity Scenario: major increase in SOC memory content forced by insufficient design, reuse productivity increases (Japan) ITRS meeting, San Francisco, 2000

11. SOC Low Power Total Power Trend with No Low Power Solution Total Power Trend with Low Power Solution Scenario to keep 3W ITRS, meeting in Leuven

12. Goal: “Living Roadmap” • Transparent, self-consistent Roadmap • Documentation of “algorithmic” relationships within, between different parts of the Roadmap • Some relationships or derivations inherently difficult to capture, e.g., Max Litho Field Size derivation -- but these can be “hard-wired” • Sanity checks (e.g., cost or power), “which rule does not belong” checks, etc. • Easier calibration, adjustment to actual design or technology data points • Initial focus: ORTCs • Interactions with other ITWGs, panels (chip size, etc.)

13. Living Roadmap Framework • GSRC Technology Extrapolation (GTX) Engine http://vlsicad.cs.ucla.edu/GSRC/GTX • Open source, allows flexible capture and study of impact of modeling choices, optimization constraints

14. System Drivers (SoC) Chapter Proposal • Proposal: Evolve from SoC Chapter in 1999 ITRS • Rationale • “SOC” is too specific; ITRS should not perpetually contain such a chapter • Terms such as ASIC, MPU (with all their flavors) are not well-defined in the ITRS front material • Should set context: “what is consuming the silicon?” with as concrete definitions as possible (replace SoC chapter) • Four driver classes (proposed starting point) • Analog/RF/MEMS • ASIC = compiled HDL  gates • High-volume custom = P, DSP, embedded memories, reprogrammable • SoC = high integration, low cost, low TTM • Design, PIDS, Interconnect, Test, Packaging, other TWGs • Under consideration by IRC

15. Design Chapter Organization - Proposal • Five areas of Design • Design Process • Infrastructure, design process metrics, … • System-Level Design • Designing the system • Infrastructure for design IP reuse • Functional Verification • System-level, RT-level, … • Logical-Physical-Circuits • Circuits includes “DSM effects”, hard-IP reuse/migration, etc. • Test

16. Design ITWG Schedule (Tentative) • US Design DTWG - initial draft responsibility • US Design TWG (with Test representation) met November 5 • Design ITWG - meeting December 12 IEDM • US Design DTWG - teleconference December 13 • First drafts of new text - January 31 • Meeting (ITWG, DTWG) in February

17. Cross-TWG Representatives Test Tim Cheng Interconnect Dennis Sylvester Assembly & Packaging Dennis Sylvester Lithography Andrew Kahng Global Interconnect WG Peter Bannon Chip Size WG Andrew Kahng Frequency/Power lines Mark Horowitz Layout Density Rich Howard Pkg Pins/Balls Sylvester/Kahng

18. Heights to which technology can take us Slippery slope if we’re not careful The Roadmap Ahead . . .

19. The votes have been counted. Again and again. It’s time to start the transition to the2001 ITRS. I support the rule of law (Moore’s Law, that is). Let’s count every dimple on the wafer (on selected chips).