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Lecture 9 RTL Design Methodology

Lecture 9 RTL Design Methodology. Structure of a Typical Digital System. Data Inputs. Control Inputs. Control Signals. Datapath ( Execution Unit ). Control ler (Control Unit ). Status Signals. Data Outputs. Control Outputs. Hardware Design with RTL VHDL. Interface. Pseudocode.

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ASM block

The state box represents the state in the FSM, and the output in the state box describes the desired output values when the FMS enters this state (i.e. the Moore outputs ). The decision box tests an input condition to determine the exit path of the current ASM block.

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Lecture 9 RTL Design Methodology

ASM block