PowerPC based reliable computer

1. טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל PowerPC based reliable computer Midterm presentation Students: Guy Derry Gil Wiechman Instructor: Isaschar Walter Winter 2003

2. Problem: In space, VLSI devices are exposed to large amounts of cosmic radiation, since there is no atmosphere to filter it out. Therefore, the MTBF of electronic equipment in space is greatly reduced. Solution: Design of redundant devices to be used in space systems, hence increasing overall system reliability.

3. Project goals • Develop a working prototype of a satellite computer, implementing the peripheral device monitoring and operation algorithm. • Examine policies of managing redundant peripherals and select one. • Implement the chosen algorithm on the Virtex II Pro FPGA board

4. Project Assumptions In this project, we assume correct operation of the software, on a correctly operating single processor. The issue of multiple processors handling is examined under a different project, running concurrently to ours.

5. Implementation tools The project is implemented using the following tools: Synplify Pro

6. PLB Monitor (master) Transparent Corrector Transparent Corrector P1 P2 P3 Memory-fault Monitor PLB Monitor (slave) M1 M2 M3 General block diagram (opt. I) PPC405 PLB Arbiter

7. State description: Countdown: count N clock cycles Read_Even / Read_Odd : Read from slave unit address #1/2. If expected value is not received, try again until success or three consequent failures. Reset_Bus: Reset the bus, and read it. If bus is not reset to zero, try again until success or three consequent failures. Countdown Read_Even Read_Odd Reset_Bus ALL TESTS:3 consequent failures  Interrupt to CPU. PLB Monitor - Master

8. PLB Monitor - Slave While (1) { While ( Addr_On_Bus != Addr1 && Addr_On_Bus != Addr2 ); If ( Addr_On_Bus == Addr1 ) Write_To_Bus(0xAAAAAAAA); Else /* Addr_On_Bus == Addr2 */ Write_To_Bus(0x55555555); }

9. Transparent Corrector Peripheral1 Bus / Outside World Peripheral2 Peripheral3 Maj(P1,P2,P3) = P1P2 + P1P3 + P2P3

10. Memory-Fault Monitor Description: Sits on PLB and acts as a “smart” memory controller. When ‘write’ is received, write to all four memory banks. For each one, read and write until assured that correct result is stored in memory (in case on failed memory, mark in chart and shut down). When ‘read’ is received, read from three highest rated memory banks, and output the bitwise majority vote. Schematics: T.B.D.

11. LUT P1 P2 P3 PMon PMon PMon P1 P2 P3 Memory-fault Monitor PLB Monitor (slave) PLB Monitor (master) M1 M2 M3 General block diagram (opt. II) PPC405 PLB Arbiter

12. Peripheral Monitor (PMon) Description: This monitor is operated once in N clocks. The Processor (via software) requests test. A test command is sent to each peripheral, and the monitor compares expected data with actual data going out of the peripheral. In case of a match – the rating for the given peripheral is increased; otherwise – it is decreased. The rating is kept on a LUT (in the form of a state-machine), and the software now maps the most highly rated peripheral as the active peripheral until the next test.

13. Project progress report – Qtr. I • Wk. I: Study the PPC405 Processor core • Wk. II: Study the Virtex-II Pro component design • Wk. III: Get familiar with VHDL development environment • Wk. IV: Write a “Hello, world!” program for the Virtex-II Pro

14. Project progress report – Qtr. I (cont.) • Wk. V: Expand programming abilities; study & work with peripheral interface • Wk. VI: Continue working on FPGA / Study the monitoring algorithm • Wk. VII: Continue working on FPGA / Begin implementing the monitoring algorithm

15. Project Schedule – Qtr. II • Wk. VIII: Understand PPC programming • Wk. IX: Implement Master & Slave PLB monitors • Wk. X: Test & incorporate PLB monitor units into design • Wk. XI: Implement & test Transparent correctors

16. Project Schedule – Qtr. II (cont.) • Wk. XII: Incorporate Transparent correctors into the design • Wk. XIII: Write a test program for the partial design and implement simple error generating units. • Wk. XIV: Incorporate & synthesize full system (with non-redundant memory) and run tests.

17. Project schedule - First Semester Goals • Synthesize a full system incl. peripherals, memory & PLB monitors. • Multiple peripheral unit operation ability • Detect a faulty PLB & send interrupt accordingly

18. Project schedule - Second Semester Goals • Most of the work on memory redundancy will be performed during the second semester • DCR monitoring will be done on second semester • Final goal: fully operative system incl. a simulation of an identification and correct operation in case of a faulty device