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PowerPC Introduction

PowerPC Introduction. Sun Xulin. Agenda. PowerPC History PowerPC ARCH PowerPC for VxWorks How to add a new PowerPC variant - PPC476 - PPC465. PowerPC. VxWorks Overview HIG(BSPs, drivers, architecture) Architecture( PowerPC , ARM, MIPS, X86,COLDFIRE, SPARC…).

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PowerPC Introduction

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  1. PowerPC Introduction Sun Xulin

  2. Agenda • PowerPC History • PowerPC ARCH • PowerPC for VxWorks • How to add a new PowerPC variant - PPC476 - PPC465 CONFIDENTIAL

  3. PowerPC • VxWorks Overview • HIG(BSPs, drivers, architecture) • Architecture(PowerPC, ARM, MIPS, X86,COLDFIRE, SPARC…) CONFIDENTIAL

  4. PowerPC History • POWER: Power Optimization With Enhanced RISC - POWER is a RISC instruction set architecture designed by IBM - 1990年被 RS 或 RISC System/6000 UNIX 工作站采用 - POWER1 … POWER7… • PowerPC（PC: performance computing) - based on IBM's earlier POWER architecture - created by the 1991 Apple–IBM–Motorola alliance, known as AIM. 最初目的，用在PC(苹果机比较成功 1994-2006)反击Wintel。 第一个PowerPC芯片601 CONFIDENTIAL

  5. PowerPC History – cont • AIM alliance break - 2004 Motorola剥离芯片业务成立Freescale - IBM卖掉Embedded processor给AMCC - 2005 Apple转向Intel processor • New Power.org - open standards 被IEEE统一管理 - 成员包括IBM Freescale AMCC - IBM 主做POWER,Game consoles - Freescale/AMCC主做Embedded processor - POWER Architecture: PowerPC,Cells,POWER - unified ISA specification CONFIDENTIAL

  6. PowerPC History – cont • BookE - PowerPC for Embedded Environment - 2000 年开始，摩托罗拉和 IBM 的 PowerPC 芯片都开始遵循 Book E 规范 • BookE vs AIM - Book E defines more flexible interrupt and memory management models. - Segment and block address translation (BAT) registers are gone - Book E supports the use of auxiliary processing units - Registers different - Instructions set different - Interrupts & exceptions different CONFIDENTIAL

  7. PowerPC Market • PowerPC - 网络和存储设备 - 从视频游戏终端、多媒体娱乐系统，到数字助手和蜂窝电话，再到基站和 PBX 开关 - 桌面系统中也会有 PowerPC • POWER - IBM 的很多服务器、工作站和超级计算机的主要处理器 • Cell - 游戏控制器 CONFIDENTIAL

  8. PowerPC History – evolution CONFIDENTIAL

  9. PowerPC ARCH – Levels • Book I User instruction set architecture(UISA) 定义通用于所有 PowerPC 实现的用户指令和寄存器的基本集合，非特权指令 • Book II Virtual Environment Architecture (VEA) 定义附加的用户级功能，如高速缓存管理、原子操作和用户级计时器支持 • Book III Operating Environment Architecture (OEA) 定义操作系统级需要和使用的操作 CONFIDENTIAL

  10. PowerPC ARCH – Registers • 32 general purpose registers • 32 floating-point registers • SPRs - LR&CTR&CR … • MSR - for AIM - processor state: user mode or supervisor mode - external interrupt enable/disable - MMU enable/disable - float-point enable/disable - endian select - reset vector prefix: 0xFFF0_0100 or 0x0000_0100 CONFIDENTIAL

  11. PowerPC ARCH – Registers Usage • EABI – Embedded Application Binary Interface CONFIDENTIAL

  12. PowerPC ARCH – Stack • No push/pop instruction for PowerPC • EABI conventions various data into the stack frame in a consistent manner. CONFIDENTIAL

  13. PowerPC ARCH – Interrupt & Exceptions • 异步不可屏蔽中断 - 0x200, 0x100(for AIM) • 异步可屏蔽中断 - 0x500, dec timer • 同步不精确中断 - 0x800(floating-point) • 同步精确中断 - all except above CONFIDENTIAL

  14. PowerPC ARCH – Interrupt & Exceptions CONFIDENTIAL

  15. PowerPC ARCH – Interrupt & Exceptions CONFIDENTIAL

  16. PowerPC ARCH – Interrupt & Exceptions CONFIDENTIAL

  17. PowerPC ARCH – MMU • MMU - Memory Management Unit - Implement address translation and protection • TLB - Translation Lookaside Buffer • Supported address translation for 60x - Page address translation - BAT - Real addressing mode • Supported address translation for BookE - Static Tlb - Dynamic Tlb CONFIDENTIAL

  18. PowerPC ARCH – Address Translation Mechanisms(AIM) CONFIDENTIAL

  19. PowerPC ARCH – TLB Match Process(440) CONFIDENTIAL

  20. PowerPC for VxWorks – Supported Processors • IBM/AMCC/LSI - PPC403 - PPC405 - PPC440 - PPC465(newly added by CDC) - PPC476(newly added by CDC) • FREESCALE/IBM - PPC603 - PPC604(IBM 7XX) - PPC85XX(including P4080) CONFIDENTIAL

  21. PowerPC for VxWorks – Build Mechanism • Make CPU=PPC32 TOOL=<xxx> • TOOL could be: - diab/sfdiab/e500v2diab - gnu/sfgnu/e500v2gnu • Build library - target\lib - target\lib_smp - target\precomp(预编译) CONFIDENTIAL

  22. PowerPC for VxWorks – FPU • FPU – Floating Point Unit • Available on PowerPC families - PPC440(some variants)/PPC465/PPC476 - PPC60X - PPC970 - PPC85XX(e500mc only) CONFIDENTIAL

  23. PowerPC for VxWorks – Architecture consideration • Byte Order - big endian • Branch Prediction - available for MPC85XX - ensure proper DDR controller configuration - ensure proper LAWs configuration - ensure proper TLBs cofiguration • Long jumping support - bl & bla by a signed 26-bit offset +/- 32 MB - INCLUDE_EXC_EXTENDED_VECTORS - hypervisor consider CONFIDENTIAL

  24. PowerPC for VxWorks – AIM • AIM – Architecture Independent Model • Provides an abstraction layer between OS and architecture dependent hardware • AIM for MMU & CACHE& FPU - Directory: target\src\aim - MMU: aimMmuLib.c - CACHE: aimCacheLib.c - FPU: aimFppLib.c CONFIDENTIAL

  25. PowerPC for VxWorks – AIM cont • Available architectures for AIM - PowerPC & MIPS • Not available architectures for AIM - X86 & ARM • PowerPC families implemented AIM for MMU - PPC405/440/465/476/MPC85XX • PowerPC families implemented AIM for CACHE - PPC465/476 - PPC603/604/970/MPC85XX CONFIDENTIAL

  26. PowerPC for VxWorks – MMU • Bootloader - not install MMU Lib, just use static TLB or BAT. - PPC440, cache is disabled. • vxWorks - call usrMmuInit install MMU lib. - cache must be enabled. CONFIDENTIAL

  27. PowerPC for VxWorks – Interrupt vector • Interrupt Vector Table - at physical address zero. - AIM: MSR[ip] bit determine vector table 0xfff00000 or 0 - BookE: IVPR & IVOR • Boot Sequencing - BookE(Why bootrom size is 1M? ) Reset exception(0xfffffffc) -> resetEntry(0xfffff800)->romInit(0xfff00000) - AIM romInit(0xfff00100) CONFIDENTIAL

  28. How to add a new PowerPC CPU variant • Find out corresponding CPU family (60x, BookE…) • Find out the differents with previous CPU family. - MMU - Cache • If there are newly instructions added, if yes, Complier need to change also. • Series Makefile updated. CONFIDENTIAL

  29. Differents between PowerPC 440/465/476 • MMU & Cache Different • Different PLB used for these cores - PPC440: PLB4 - PPC465: PLB5 - PPC476: PLB6 • Totally same modules between these Cores - Interrupts and exceptions - Timer facilities - Debug facilities CONFIDENTIAL

  30. PowerPC476 – Overview • Power Instruction Set Architecture (ISA) 2.05 • 4-issue, 5-pipeline and separate FP pipeline, superscalar, 32-bit RISC with 42-bit real RA space • 32-bit DCR address space with new instructions • Memory Coherency for multiprocessing system • 1024 UTLB with HASHed index • new instructions (lwsync,tlbivax,mtdcrx/mfdcrx) • Power Control Features (MSR[WE]) • FPU CONFIDENTIAL

  31. PowerPC476 – Core block diagram CONFIDENTIAL

  32. PowerPC476 – MMU implement • 1024 unified TLB entries, 6 Bolted UTLB entries, 8 ITLB entries and 8 DTLB entries • 49-bit virtual address(VA) formed by 32-bit effective address(EA), 1-bit address space (AS) and 16-bit PID • 4TB (42-bit) real address (RA) space • implementation method of static TLB - hardware assistance: only 6 bolted entries can be used - software: more entries but more bolted entries • hardware assistance mode - static TLBs only can be bolted entries - hardware selects the way to be written into in DTLB/ITLB miss handlers • software mode CONFIDENTIAL

  33. PowerPC476 – MMU implement CONFIDENTIAL

  34. PowerPC476 - MMU implement • mmu476Lib.c provides the architecture dependent routines - Implement MMU functions for AIM layer - Staitic TLB initialization for vxWorks - MMU optimization • mmu476ALib.s contains assembly-language functions common to all 476-derived MMUs. CONFIDENTIAL

  35. PowerPC476 – Cache implement CONFIDENTIAL

  36. PowerPC476 – Cache implement • cacheAim476Lib.c contains architecture-specific cache library - Cache size & cache line sizeprovided - cacheDisable/Enable - cacheDma operations CONFIDENTIAL

  37. PowerPC465 - Overview • Book-E Enhanced Power Architecture processor cores • 2-issue, 4-pipeline • Four-bit extended real address for 36-bit (64GB) addressability • 32-bit DCR address space with new instructions • Memory Coherency for multiprocessing system • 64-entry, fully associative unified TLB array • new instructions (mtdcrx/mfdcrx) • FPU CONFIDENTIAL

  38. PowerPC465 – Core block diagram CONFIDENTIAL

  39. PowerPC465 – Arch Works • Added cache AIM implement for PPC465 ARCH - cacheAim465Lib.c - cacheAim465ALib.s • MMU440 Lib modification - Add 1GB page size to UTLB - New TLB entry attributes - Fixed Address Region CONFIDENTIAL

  40. Reference Materials • Others PowerPC materials • Links http://www.power.org http://www.ibm.com/chips/power http://www.freescale.com/powerp http://www.freescale.com/qoriq http://www.amcc.com/embedded CONFIDENTIAL

  41. Win

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