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Shift Register

Shift Register. Section 6.1-6.2. In-Class Exercise. Load=“1”→Update. I 0 is fed to DFF when Load is a 1. “0”. “1”. “1”. “0”. “I 0 ”. “I 0 ”. Load=“0”→Hold!. A 0 is fed to DFF when Load is a 0. So the output is holding !. “1”. “0”. “0”. “A 0 ”. “A 0 ”. “0”.

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Shift Register

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  1. Shift Register Section 6.1-6.2

  2. In-Class Exercise

  3. Load=“1”→Update I0 is fed to DFF when Load is a 1. “0” “1” “1” “0” “I0” “I0”

  4. Load=“0”→Hold! A0 is fed to DFF when Load is a 0. So the output is holding! “1” “0” “0” “A0” “A0” “0” We will revisit this idea when we study the universal shift register.

  5. S0=0, S1=0 [No Change Mode] S0=0, S1=0

  6. S0=1, S1=0 [Shift Right Mode] S1=0 , S0=1

  7. S0=0, S1=1 [Shift Left Mode] S1=1 , S0=0

  8. S0=1, S1=1 [Parallel Load Mode] S1=1 , S0=1

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